Macrocell Architectures for Product Term Embedded Memory Arrays

Lin, Ernie; Wilton, Steven J. E.

doi:10.1007/3-540-44687-7_6

Cited by 5 publications

(6 citation statements)

References 7 publications

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“…The post-mapping four-LUT count of each benchmark circuit was obtained by counting the number of nodes in the four-LUT partition output of hybridmap. It can be seen that, as the number of available PLAs increases, hybridmap achieves better LUT coverage than the approach presented in [2]. A maximum improvement of 22% was achieved for 10 PLAs per device ( ).…”

Section: B Comparisons To Previous Workmentioning

confidence: 94%

“…A maximum improvement of 22% was achieved for 10 PLAs per device ( ). The improved PLA packing density obtained by hybridmap is attributed mainly to two of the procedures available in hybridmap but not in [2]: subgraph-based logic extraction accentuated by hill climbing and Pterm estimation targeting Apex20KE devices.…”

Section: B Comparisons To Previous Workmentioning

confidence: 96%

“…Lin and Wilton [2] developed a technology mapping algorithm targeting hybrid architectures. Input to the PLA-mapping algorithm is first pre-mapped to four-LUTs using LUT technology mapping tools [15].…”

Section: Related Workmentioning

confidence: 99%

“…These reconvergent paths could be covered with a single PLA subgraph boosting LUT savings. Alternative PLA covering approaches [2], [22], [27] do not identify reconvergent paths that exceed PLA I/O limits. In our approach, a hill-climbing phase extends forward and inverse traversal beyond the point where PLA input and output limits are exceeded with the expectation that the subgraph will reconverge.…”

Section: Subgraph Generationmentioning

confidence: 99%

“…The target architecture for both cases is the Apex20KE architecture with PLA counts ranging from 1 to 10. The input to the PLA mapping approach described in [2] is a four-LUT mapped circuit from which PLA subgraphs are extracted based on a search algorithm. The uncovered nodes in the design at the end of the PLA mapping process are counted to obtain the final LUT count.…”

Section: B Comparisons To Previous Workmentioning

confidence: 99%

See 4 more Smart Citations

Technology mapping algorithms for hybrid fpgas containing lookup tables and plas

Krishnamoorthy

Tessier

2003

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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show abstract

Section: B Comparisons To Previous Workmentioning

confidence: 94%

Section: B Comparisons To Previous Workmentioning

confidence: 96%

Section: Related Workmentioning

confidence: 99%

Section: Subgraph Generationmentioning

confidence: 99%

Section: B Comparisons To Previous Workmentioning

confidence: 99%

See 3 more Smart Citations

Technology mapping algorithms for hybrid fpgas containing lookup tables and plas

Krishnamoorthy

Tessier

2003

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Using Multiplexers for Control and Data in D-Fabrix

Stansfield¹

2003

Field Programmable Logic and Application

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The architecture of dual-mode FPGA embedded system blocks

Lin

Wilton

Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)

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Recently, it has been shown that unused on-chip memories can be valuable when they are used to implement logic.This paper explores how different memory architecture parameters affect its ability to implement logic in dual-mode FPGA Embedded System Blocks. It is shown that the optimum memory architecture has a depth of 32 or 64 words, and that each word should contain 16 bits. IntroductionTraditionally, applications of field-programmable gate arrays (FPGAs) have been limited to small glue-logic subcircuits. As the logic capacity and speed of FPGAs increase, however, FF'GAs are becoming the technology of choice for implementing large systems. The requirements of larger systems differ from smaller systems, since larger system typically require access to memory. As a result, most modem FPGAs now contain large embedded RAM arrays [ 1, 21. These arrays provide dense implementations of storage, but require the FPGA vendor partition the chip into logic and storage regions when the FPGA is designed. Since circuits have widely varying requirements for memory resources, this "average case" partitioning may result in poor device utilization in logic-intensive applications. More specifically, if memory is not used completely or not at all, the chip area devoted to memory is wasted.However, this area need not be wasted, if unused memory arrays are used to implement logic. Unused memories can be configured as large ROM multiple-input, multiple-output lookup tables. Wilton's SMAP [3] and Cong and Xu's EMBPack [4] are two existing algorithms for mapping logic to unused memory arrays.These algorithms work well if there are only a small number of memory arrays, but as the number of arrays increase, the efficiency of the memories when implementing logic decreases [3]. To improve the logic density when there are a large number of arrays, the APEX20k architecture has enhanced memory arrays called Embedded System Blocks (ESB) [5]. Each ESB can be configured in one of two modes: it can act as a conventional memory, which can be used for storage or logic, or it can act as a programmable array logic (PAL) block for implementing functions as a sum of products. An algorithm, pMapster, which maps circuits to this dual-mode architecture, was presented in [6].While the amount of logic that can be packed into each ESB depends on the quality of the CAD algorithm used to perform the packing [6], the architecture of the ESB can have a very dramatic effect on the achievable packing density. A memory that is too small will result in a small amount of logic being packed into it, while a memory that is too large will result in underutilization. In this paper, we seek to find the optimum width and depth for these ESBs. Comparison to Previous WorkAn FPGA with dual-mode embedded system blocks is essentially a type of hybrid FPGA as described in [7] in that it contains both lookup-tables (the logic resources) and product-term blocks (the ESBs configured in product-term mode). In [7], the optimum architecture for such an FPGA is sought. Our focus differs ...

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Macrocell Architectures for Product Term Embedded Memory Arrays

Cited by 5 publications

References 7 publications

Technology mapping algorithms for hybrid fpgas containing lookup tables and plas

Technology mapping algorithms for hybrid fpgas containing lookup tables and plas

Using Multiplexers for Control and Data in D-Fabrix

The architecture of dual-mode FPGA embedded system blocks

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