Magneto-Electric Approximate Computational Circuits for Bayesian Inference

Kulkarni, Sourabh; Bhat, Sachin; Khasanvis, Santosh; Moritz, Csaba Andras

doi:10.1109/icrc.2017.8123678

Cited by 2 publications

(1 citation statement)

References 15 publications

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“…To increase the resolution, it is needed to change the abovementioned flat linear representation that increases area linearly (where a single probability value requires multiple physical signals). To this end, as shown in Figures 5H,I , another S-MTJ-based circuit paradigm leveraging physical equivalence with a new approximate circuit-style has been reported ( Kulkarni et al, 2017a ), where the computation resolution is 1/( n M ) where M is the number of Radix segments where each segment is composed of flat elements. This is a new direction on scaling computational resolution, which is a hybrid method for representing probabilities, aiming to provide networks with millions of random variables.…”

Section: New Computing Architecture With Nonvolatile Memory Elements For Bayesian Network Implementationmentioning

confidence: 99%

Brain-Inspired Hardware Solutions for Inference in Bayesian Networks

Bagheriye

Kwisthout

2021

Front. Neurosci.

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The implementation of inference (i.e., computing posterior probabilities) in Bayesian networks using a conventional computing paradigm turns out to be inefficient in terms of energy, time, and space, due to the substantial resources required by floating-point operations. A departure from conventional computing systems to make use of the high parallelism of Bayesian inference has attracted recent attention, particularly in the hardware implementation of Bayesian networks. These efforts lead to several implementations ranging from digital circuits, mixed-signal circuits, to analog circuits by leveraging new emerging nonvolatile devices. Several stochastic computing architectures using Bayesian stochastic variables have been proposed, from FPGA-like architectures to brain-inspired architectures such as crossbar arrays. This comprehensive review paper discusses different hardware implementations of Bayesian networks considering different devices, circuits, and architectures, as well as a more futuristic overview to solve existing hardware implementation problems.

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Section: New Computing Architecture With Nonvolatile Memory Elements For Bayesian Network Implementationmentioning

confidence: 99%

Brain-Inspired Hardware Solutions for Inference in Bayesian Networks

Bagheriye

Kwisthout

2021

Front. Neurosci.

View full text Add to dashboard Cite

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Architecting for Artificial Intelligence with Emerging Nanotechnology

Kulkarni

Bhat

Moritz

2021

J. Emerg. Technol. Comput. Syst.

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Artificial Intelligence is becoming ubiquitous in products and services that we use daily. Although the domain of AI has seen substantial improvements over recent years, its effectiveness is limited by the capabilities of current computing technology. Recently, there have been several architectural innovations for AI using emerging nanotechnology. These architectures implement mathematical computations of AI with circuits that utilize physical behavior of nanodevices purpose-built for such computations. This approach leads to a much greater efficiency vs. software algorithms running on von Neumann processors or CMOS architectures, which emulate the operations with transistor circuits. In this article, we provide a comprehensive survey of these architectural directions and categorize them based on their contributions. Furthermore, we discuss the potential offered by these directions with real-world examples. We also discuss major challenges and opportunities in this field.

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Magneto-Electric Approximate Computational Circuits for Bayesian Inference

Cited by 2 publications

References 15 publications

Brain-Inspired Hardware Solutions for Inference in Bayesian Networks

Brain-Inspired Hardware Solutions for Inference in Bayesian Networks

Architecting for Artificial Intelligence with Emerging Nanotechnology

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