MaizeRouter: Engineering an effective global router

Moffitt,

doi:10.1109/aspdac.2008.4483946

Cited by 54 publications

(52 citation statements)

References 22 publications

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“…The results are given in Table III. We have also conducted the same experiment on several selected benchmarks on the output of MaizeRouter [10]. In these experiments, we iteratively reduced the vertical and horizontal capacity of the ISPD98 benchmarks until we got overflows while running them through MaizeRouter.…”

Section: Nc Phasementioning

confidence: 99%

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Efficient Rerouting Algorithms for Congestion Mitigation

Chaudhry

Asad

Sprintson

et al. 2009

2009 IEEE Computer Society Annual Symposium on VLSI

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Abstract-Congestion mitigation and overflow avoidance are two of the major goals of the global routing stage. With a significant increase in the chip size and routing complexity, congestion and overflow have become critical issues in physical design automation. In this paper we present several routing algorithms for congestion reduction and overflow avoidance. Our methods are based on ripping up nets that go through the congested regions and replacing them with congestion-aware Steiner trees. We propose several efficient algorithms for finding congestion-aware Steiner trees and evaluate their performance using the ISPD routing benchmarks. We also show that the novel technique of network coding contributes to further improvements in routability and reduction of congestion. Accordingly, we propose an algorithm for identifying efficient congestion-aware network coding topologies and evaluate its performance.

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Section: Nc Phasementioning

confidence: 99%

“…Reference [9] proposes an approach based on the Lagrangian multiplier technique. An effective edge shifting technique is presented in [10]. Most of these previous works adopt the strategy of rip-up-and-reroute.…”

Section: A Previous Workmentioning

confidence: 99%

Efficient Rerouting Algorithms for Congestion Mitigation

Chaudhry

Asad

Sprintson

et al. 2009

2009 IEEE Computer Society Annual Symposium on VLSI

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“…The key of CADA is to control congestion, which is achieved by performing 2D directive-aware routing and directive assignment. In this work, a 2D-routing engine adapted from MaizeRouter [6] is used but the maze routing in MaizeRouter is replaced by extreme edge shifting (refer to [6] for details about this technique) to improve the speed; however, it should be pointed out our flow can work with any other 2D routing engine. To deal with directives in 2D routing, we use the progressive projection method in [15] as discussed in Sec.…”

Section: A Algorithmmentioning

confidence: 99%

CATALYST: Planning Layer Directives for Effective Design Closure

Wei

Sze

et al. 2013

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2013

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Abstract-For the last several technology generations, VLSI designs in new technology nodes have had to confront the challenges associated with reduced scaling in wire delays. The solution from industrial back-end-of-line process has been to add more and more thick metal layers to the wiring stacks. However, existing physical synthesis tools are usually not effective in handling these new thick layers for design closure. To fully leverage these degrees of freedom, it is essential for the design flow to provide better communication among the timer, the router, and different optimization engines. This work proposes a new algorithm, CATALYST, to perform congestion-and timing-aware layer directive assignment. Our flow balances routing resources among metal stacks so that designs benefit from the availability of thick metal layers by achieving improved timing and buffer usage reduction while maintaining routability. Experiments demonstrate the effectiveness of the proposed algorithm. I. INTRODUCTIONPhysical synthesis is a critical component of modern design methodologies, enabling timing closure at the physical design stage. Technology scaling brings new challenges and opportunities to physical synthesis. Wire resistance per unit length increases quadratically with technology scaling and results in significant increases in wire delay. However, recent work [1], [2] shows that the availability of thicker wires in higher metal layers could potentially relieve this problem. At 65 nm technology, there are four 1× layers, three 2× layers and two 4× layers (Fig. 3). On a 2× layer, the single-width wires are 2× thicker and 2× wider than those on 1× layer, and therefore the per-unit wire resistance is reduced by roughly 4× (the per-unit capacitance is roughly similar across all layers, which is ensured by design rules including wire spacing and process specifications such as inter-layer dielectric thickness), greatly compensating for technology scaling effects. On the 2× [4×] layer, signals can roughly go 1.7× [2.5×] faster, with 2× [4.4×] reduction in buffer resources. Therefore, the difference in wire delays in different layers provides another dimension to timing optimization, beyond gate/wire sizing and buffering. Assigning timingcritical nets to thick layers can reduce area/power and improve timing closure by reducing delays and the buffer count. As illustrated in Fig. 1, the slack for a two-pin net A on a 4× layers is improved from -10 ps to 10 ps as compared to the corresponding route on the 1× layer, and the number of buffers is reduced from 7 to 1. Moreover, by using thick layers wisely, it could be shown that a 31% reduction on buffer area averaged over several industrial circuits can be achieved (Sec. VI-B). On the other hand, there are limited resources on thicker layers, and if too many nets are assigned to thicker layers, the design may not be routable or have large post-routing timing degradation.

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“…The above two-step approach is adopted by the majority of recent academic GR procedures [8], [23], [10], [26], [31]. However, neglecting the via cost when solving the 2-D routing problem may lead to significant degradation in solution quality.…”

Section: B Multi-layer Global Routingmentioning

confidence: 99%

“…Specifically, among the two categories of concurrent and sequential procedures, the latter became very popular recently to handle large-sized problem instances [8], [31], [23], [22], [26], [9]. However, an inherent downside of the sequential procedures is their high dependence on properties such as the ordering of the nets or the definition of empirical cost functions.…”

Section: Introductionmentioning

confidence: 99%

GRIP: Global Routing via Integer Programming

Davoodi

Linderoth

2011

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-This work introduces GRIP, a global routing technique via integer programming. GRIP optimizes wirelength and via cost directly without going through a traditional layer assignment phase. Candidate routes spanning all the metal layers are generated using a linear programming pricing phase that formally accounts for the impact of existing candidate routes when generating new ones. To make an integer-programmingbased approach applicable for today's large-scale global routing instances, the original problem is decomposed into smaller subproblems corresponding to rectangular subregions on the chip together with their net assignments. Route fragments of nets that fall in adjacent subproblems are connected in a flexible manner. In case of overflow, GRIP applies a second-phase optimization that explicitly minimizes overflow. By using integer programming in an effective manner, GRIP obtains high-quality solutions. Specifically, for the ISPD 2007 and 2008 benchmarks, GRIP obtains an average improvement in wirelength and via cost of 9.23% and 5.24%, respectively, when compared to the best result in the open literature.

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MaizeRouter: Engineering an effective global router

Cited by 54 publications

References 22 publications

Efficient Rerouting Algorithms for Congestion Mitigation

Efficient Rerouting Algorithms for Congestion Mitigation

CATALYST: Planning Layer Directives for Effective Design Closure

GRIP: Global Routing via Integer Programming

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