Making Write Less Blocking for Read Accesses in Phase Change Memory

Yue, Jianhui; Zhu, Yan

doi:10.1109/mascots.2012.39

Cited by 20 publications

(13 citation statements)

References 21 publications

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“…Hence, NVM modules are restricted to writing a limited amount of data at once, which in turn increases the write latency and impacts performance [14]. Furthermore, since a single write access usually involves both set and reset, the latency of the write operation is determined by the longest latency cell write, creating a bottleneck for individual write operations [21].…”

Section: -Bit Fpc Values (Inclusive Of 3-bit Prefix Indicated In Red)mentioning

confidence: 99%

“…Existing solutions based on data-encoding [5], write scheduling [6][7][8][9], data-migration using address translation [10][11][12], and architectural improvements [13,14] focus exclusively on improving either NVM latency, power/energy, or endurance. However, bit-write reduction techniques can address these limitations simultaneously.…”

Section: Fnw and Fpc: Backgroundmentioning

confidence: 99%

“…However, NVMs present new challenges in comparison to DRAM: asymmetric read/write access latencies, higher power/energy requirements, and limited endurance, which impede their large-scale adoption in computing systems [1][2][3]. To overcome these problems, a broad set of solutions that rely on dataencoding [5], write scheduling [6][7][8][9], data-migration using address translation [10][11][12], and architectural improvements [13,14] have been proposed. However, these techniques address either NVM latency, power/energy, or endurance explicitly; this potentially limits their effectiveness in practice.…”

Section: Introductionmentioning

confidence: 99%

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Palangappa

Mohanram

2015

Proceedings of the 25th Edition on Great Lakes Symposium on VLSI

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This paper proposes Flip-Mirror-Rotate (FMR), an architecture for bit-write reduction and endurance enhancement in emerging nonvolatile memories (NVMs). FMR comprises three components: adaptive Flip-N-Write (aFNW), Mirror-N-Write (MNW), and Rotate-N-Write (RNW). aFNW and MNW focus on word-level bit-write reduction, which reduces NVM dynamic energy while also improving endurance. RNW is an intra-word wear leveling scheme that operates at cache line granularity. The proposed FMR architecture is integrated with frequent pattern compression (FPC) to simultaneously reduce bit-writes and wear in NVMs. Trace-based simulations of the SPEC CPU2006 benchmarks show that for the same memory overhead and < 1% loss in memory bandwidth, FMR reduces bit-writes (dynamic energy) by 48% (29%) in comparison to classical read-modify-write (DCW), 39% (13%) in comparison to Flip-N-Write (FNW), and 21% (14%) in comparison to FPC. Simultaneously, FMR also reduces the peak bit-writes per cell by 47% in comparison to DCW, 34% in comparison to FNW, and 47% in comparison to FPC, improving NVM endurance.

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Section: -Bit Fpc Values (Inclusive Of 3-bit Prefix Indicated In Red)mentioning

confidence: 99%

Section: Fnw and Fpc: Backgroundmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Flip-Mirror-Rotate

Palangappa

Mohanram

2015

Proceedings of the 25th Edition on Great Lakes Symposium on VLSI

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“…As a result, devices are restricted to writing a limited amount of data at once, iterating over the memory array to complete writes. This restriction increases the write latency, impacting performance [32]. Second, SET and RESET operations in PCM require long pulses to ensure that the material cools properly, up to hundreds of nanoseconds.…”

Section: Energy Endurance and Latencymentioning

confidence: 99%

“…This process is managed using additional ECC cells, which are incorporated into the array using the form switch method to compress each line. Additionally, Yue and Zhu propose a method for preventing write accesses from potentially blocking read accesses in PCM [32]. This method proposes a reorganization of the PCM banks called Parallel Chip PCM (PC2M).…”

Section: Improving Nvm Performancementioning

confidence: 99%

Compression architecture for bit-write reduction in non-volatile memory technologies

Dgien

Palangappa

Hunter

et al. 2014

2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)

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In this thesis we explore a novel method for improving the performance and lifetime of non-volatile memory technologies. As the development of new DRAM technology reaches physical scaling limits, research into new non-volatile memory technologies has advanced in search of a possible replacement. However, many of these new technologies have inherent problems such as low endurance, long latency, or high dynamic energy. This thesis proposes a simple compression-based technique to improve the performance of write operations in non-volatile memories by reducing the number of bit-writes performed during write accesses. The proposed architecture, which is integrated into the memory controller, relies on a compression engine to reduce the size of each word before it is written to the memory array. It then employs a comparator to determine which bits require write operations.By reducing the number of bit-writes, these elements are capable of reducing the energy consumed, improving throughput, and increasing endurance of non-volatile memories. We examine two different compression methods for compressing each word in our architecture.First, we explore Frequent Value Compression (FVC), which maintains a dictionary of the words used most frequently by the application. We also use a Huffman Coding scheme to perform the compression of these most frequent values. Second, we explore Frequent Pativ tern Compression (FPC), which compresses each word based on a set of patterns. While this method is not capable of reducing the size of each word as well as FVC, it is capable of compressing a greater number of values. Finally, we implement an intra-word wear leveling method that is able to enhance memory endurance by reducing the peak bit-writes per cell.This method conditionally writes compressed words to separate portions of the non-volatile memory word in order to spread writes throughout each word. Trace-based simulations of the SPEC CPU2006 benchmarks show a 20× reduction in raw bit-writes, which corresponds to a 2-3× improvement over the state-of-the-art methods and a 27% reduction in peak cell bit-writes, improving NVM lifetime.v Solutions to these problems must be designed before we can realize widescale adoption of any of these technologies in main memory systems. WORK OVERVIEWIn this work, we propose a compression-based architecture to reduce bit-writes and improve write energy, write latency, and write endurance in non-volatile memories (NVM). The proposed architecture, which is integrated into the memory controller, relies on a compression engine and a data comparator which work together to reduce the number of bit-writes that occur during each write access to memory. We discuss two different compression methods to be When a write access is received by the memory controller, each word is passed through the compression engine to attempt compression of the data. If the word is unable to be compressed, the memory controller writes it "as is" to the memory cells. During the write operation to the NVM cells, the memory controll...

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Address Translation Layer for Byte-Addressable Non-Volatile Memory-Based Solid State Drives

Kwon

2019

IEEE Access

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Because of the need for processing and managing the massive amounts of big data in smart/wearable devices and driverless vehicles, semiconductor companies are focusing on developing byte-addressable non-volatile memory (NVM)-based storage systems. The byte-addressable NVMs, such as phase-change memory, resistive memory, and magnetoresistive memory, are regarded as an alternative to NAND flash memories. There have been many proposals and studies on the use of NVM as main memory in the memory hierarchy. However, there has not been much academic research on using NVM as a substitute for NAND flash memories. This paper provides a system architecture for an NVM-based solid state drive based on some speculations/assumptions on the hardware characteristics of NVMs. It applies the previously proposed address-mapping algorithms of conventional solid state drives to the NVM-based solid state drives and examines their suitability. The optimization of I/O parallelism of static and dynamic address mapping algorithms is compared and analyzed. This paper also observes the effect of log block policies on the hardware characteristics of the NVMs.

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Making Write Less Blocking for Read Accesses in Phase Change Memory

Cited by 20 publications

References 21 publications

Flip-Mirror-Rotate

Flip-Mirror-Rotate

Compression architecture for bit-write reduction in non-volatile memory technologies

Address Translation Layer for Byte-Addressable Non-Volatile Memory-Based Solid State Drives

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