Managing Burstiness and Scalability in Event-Driven Models on the SpiNNaker Neuromimetic System

Abstract

Neural networks present a fundamentally different model of computation from the conventional sequential digital model, for which conventional hardware is typically poorly matched. However, a combination of model and scalability limitations has meant that neither dedicated neural chips nor FPGA's have offered an entirely satisfactory solution. SpiNNaker introduces a different approach, the "neuromimetic" architecture, that maintains the neural optimisation of dedicated chips while offering FPGA-like universal configurability. This parallel multiprocessor employs an asynchronous event-driven model that uses interrupt-generating dedicated hardware on the chip to support real-time neural simulation. Nonetheless, event handling, particularly packet servicing, requires careful and innovative design in order to avoid local processor congestion and possible deadlock. We explore the impact that spatial locality, temporal causality and burstiness of traffic have on network performance, using tunable, biologically similar synthetic traffic patterns. Having established the viability of the system for real-time operation, we use two exemplar neural models to illustrate how to implement efficient event-handling service routines that mitigate the problem of burstiness in the traffic. Extending work published in ACM Computing Frontiers 2010 with on-chip testing, simulation results indicate the viability of SpiNNaker for large-scale neural modelling, while emphasizing the need for effective burst management and network mapping. Ultimately, the goal is the creation of a library-based development system that can translate a high-level neural model from any description 123Int J Parallel Prog environment into an efficient SpiNNaker instantiation. The complete system represents a general-purpose platform that can generate an arbitrary neural network and run it with hardware speed and scale.

A Survey of Neuromorphic Computing and Neural Networks in Hardware

“…Occasionally, inter-chip communication interfaces will have their own hardware implementations, usually in the form of FPGAs [2353]- [2357]. SpiNNaker's interconnect system is one of its most innovative components; the SpiNNaker chips are interconnected in a toroidal mesh, and an AER communication strategy for inter-chip communication is used [1585], [1587], [2358]- [2366]. It is the communication framework for SpiNNaker that enables scalability, allowing tens of thousands of chips to be utilized together to simulate activity in a single network.…”

Analytical Assessment of the Suitability of Multicast Communications for the SpiNNaker Neuromimetic System

“…It has been demonstrated, however, that it provides an architecture general enough to seamlessly execute a wide range of applications [30]: from the simulation of neural non-spiking models such as the Multilayer Perceptron [31] to a variety of applications completely unrelated to neural networks: discrete simulation, many-body interaction, real-time ray-tracing, finite element analysis and analogue circuit simulation.…”

Population-based routing in the SpiNNaker neuromorphic architecture

“…Complete details of the system and of its performance can be found in [13], [14], [16], [17], [18] and [19]. Fig.…”