Managing SMT resource usage through speculative instruction window weighting

Abstract

Simultaneous multithreading processors dynamically share processor resources between multiple threads. In general, shared SMT resources may be managed explicitly, e.g. by dynamically setting queue occupation bounds for each thread as in the DCRA and Hill-Climbing policies. Alternatively, resources may be managed implicitly, i.e. resource usage is controlled by placing the desired instruction mix in the resources. In this case, the main resource management tool is the instruction fetch policy which must predict the behavior of each thread (branch mispredictions, long-latency loads, etc.) as it fetches instructions. In this paper, we present the use of Speculative Instruction Window Weighting (SIWW) to bridge the gap between implicit and explicit SMT fetch policies. SIWW estimates for each thread the amount of outstanding work in the processor pipeline. Fetch proceeds for the thread with the least amount of work left. SIWW policies are implicit as fetch proceeds for the thread with the least amount of work left. They are also explicit as maximum resource allocation can also be set. SIWW can use and combine virtually any of the indicators that were previously proposed for guiding the instruction fetch policy (number of in-flight instructions, number of low confidence branches, number of predicted cache misses, etc.). Therefore, SIWW is an approach to designing SMT fetch policies, rather than a particular fetch policy. Targeting fairness or throughput is often contradictory and a SMT scheduling policy often optimizes only one performance metric at the sacrifice of the other metric. Our simulations show that the SIWW fetch policy can achieve at the same time state-of-the-art throughput, state-of-the-art fairness and state-of-the-art harmonic performance mean. Key-words: Managing SMT Resource Usage through Speculative Instruction Window WeightingRésumé : Les processeurs SMT partagent les ressources du processeur dynamiquementà l'exécution entre les différents processus. Dans ce rapport, nous présentons une nouvelle politique d'allocation de ressources entre les processus qui permetà la fois un très haut débit et une distributionéquitable des ressources. Mots-clés : Multiflot excution simultanée

Selecting benchmark combinations for the evaluation of multicore throughput

“…The results in Figure 7 confirm that the degree of confidence of samples selected with workload stratification outper- 6 We did not apply balanced random sampling for 4 cores and 8 cores because the method we used for automatically defining a balanced sample works with the full workload population. In real situations this would not be a problem because detailed simulations are normally done after the workload sample is defined.…”

“…Among the studies using class-based workload selection, very few are fully automatic. In a recent study, Vandierendonck and Seznec use cluster analysis to define 4 classes among the SPEC CPU2000 benchmarks [6]. Van Biesbrouck et al [7] described a fully automatic method to define workloads using microarchitectureindependent profiling data.…”

“…For 4 cores and 8 cores, we have simulated 250 workloads. For a given sample size and for each sampling method 6 , we take 100 samples, each sample consisting of workloads that we have simulated with Zesto. We compute the per-sample throughput metric (here, the IPCT) for each of the 100 samples and for DIP and LRU.…”

A Real-Time Per-Thread IQ-Capping Technique for Simultaneous Multi-threading (SMT) Processors

“…These include: avoiding register allocation by predicting transient values from branch misprediction in [4], an allocation technique on write buffer for efficient resource occupation by limiting the maximal number of write buffer entries that a thread is allowed to have in [5], improving SMT fetching with an estimation of outstanding work in the system for each thread in [6], early deallocation of registers in association with cache misses in [7], and another fetch policy by considering memorylevel parallelism in [9]. None of these techniques specifically addresses the contention in the issuing stage and most come with a significant requirement in extra hardware to implement the desired intelligence.…”

Hyper-Heuristics for Performance Optimization of Simultaneous Multithreaded Processors

“…Vandierendonck and Seznec [6] propose a new fetch throttling mechanism called Speculative Instruction Window Weighting. This mechanism fetches instructions from the thread with least amount of work left in the pipeline.…”