MANTRA: A Multi-Model Neural-Network Computer

Viredaz, Marc A.; Lehmann, Christian W.; Blayo, François; Ienne, Paolo

doi:10.1007/978-1-4899-1331-9_9

Cited by 3 publications

(2 citation statements)

References 7 publications

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“…For some sequence of patterns a different behavior can be observed with respect to the original ART1, but the overall clustering behavior is still equivalent. Mathematically, the input to the F2 layer is now, (11) where L A and L B are positive parameters that play the role of the original L (and L−1) parameter. The condition must be imposed for proper system operation [2], [3].…”

Section: (A)mentioning

confidence: 99%

A real-time clustering microchip neural engine

Serrano-Gotarredona

Linares-Barranco

1996

IEEE Trans. VLSI Syst.

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This paper presents an analog current-mode VLSI implementation of an unsupervised clustering algorithm. The clustering algorithm is based on the popular ART1 algorithm [1], but has been modified resulting in a more VLSI-friendly algorithm [2], [3] that allows a more efficient hardware implementation with simple circuit operators, little memory requirements, modular chip assembly capability, and higher speed figures. The chip described in this paper implements a network that can cluster 100 binary pixels input patterns into up to 18 different categories. Modular expansibility of the system is directly possible by assembling an N×M array of chips without any extra interfacing circuitry, so that the maximum number of clusters is 18×M and the maximum number of bits of the input pattern is N×100. Pattern classification and learning is performed in 1.8µs, which is an equivalent computing power of 4.4×10 9 connections per second plus connection-updates per second. The chip has been fabricated in a standard low cost 1.6µm double-metal single-poly CMOS process, has a die area of 1cm 2 , and is mounted in a 120-pin PGA package. Although internally the chip is analog in nature, it interfaces to the outside world through digital signals, and thus has a true asynchronous digital behavior. Experimental chip test results are available, obtained through digital chip test equipment. Fault tolerance at the system level operation is demonstrated through the experimental testing of faulty chips.

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Section: (A)mentioning

confidence: 99%

A real-time clustering microchip neural engine

Serrano-Gotarredona

Linares-Barranco

1996

IEEE Trans. VLSI Syst.

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“…All these operations are used in the implementation of the Kohonen algorithm on MANTRA I and have been described in previous papers [17].…”

Section: Class Decisionmentioning

confidence: 99%

1D and 2D systolic implementations for radial basis function networks

Maria¹,

Guérin–Dugué²,

Blayo³

Proceedings of the Fourth International Conference on Microelectronics for Neural Networks and Fuzzy Systems

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In this paper]. we show that Radzal Basis Function networks can be efficiently implemented on 1Dand 2 0 systolic arrays. We dascuss such networks in the framework of probability density function approximation f o r classification problems. In fact, the most computation intensive parts of the classification process consist an calculating pattern distances. In the znitaalzsataon phase of the algorithm this involves calculatang the mutual (antra-class) distance matrix. The classafication of an anput vector mainly involves the calculataon of the distance vector between this input vector and all the learnang set vectors.The proposed implementations are 2 0 systolic, 1D pipeline and 10 parallel. Practical implementation issues are discussed for the M A N T R A machine ( 2 0 grid) and the SMART Neuro-computer (1D ring).

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FPNA: Concepts and Properties

Girau

FPGA Implementations of Neural Networks

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MANTRA: A Multi-Model Neural-Network Computer

Cited by 3 publications

References 7 publications

A real-time clustering microchip neural engine

A real-time clustering microchip neural engine

1D and 2D systolic implementations for radial basis function networks

FPNA: Concepts and Properties

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