Manufacturability demonstration of an integrated SiGe HBT technology for the analog and wireless marketplace

Ahlgren, D.; Gilbert, M.; Greenberg, D.; Jeng, Jin-Tsong; Malinowski, J.; Nguyen-Ngoc, D.; Schonenberg, K.; Stein, K.; Groves, R.; Walter, K.; Hueckel, G.; Colavito, D.; Freeman, G.; Sunderland, D.A.; Harame, D.L.; Meyerson, B.S.

doi:10.1109/iedm.1996.554115

Cited by 80 publications

(26 citation statements)

References 5 publications

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“…The SiGe base was grown using UHV/CVD. Details of the fabrication process can be found in [3]. The n-p-n layers of the intrinsic transistor and the p-type substrate form a n-p-n-p multilayer structure, making the charge collection more complicated Manuscript than in a conventional bipolar process [4].…”

Section: Simulation Of See-induced Charge Collection In Uhv/cvd Sige mentioning

confidence: 99%

Simulation of SEE-induced charge collection in UHV/CVD SiGe HBTs

Niu¹,

Cressler²,

Shoga

et al. 2000

IEEE Trans. Nucl. Sci.

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This paper presents quasi-3-D simulation results of SEE-induced charge collection in UHV/CVD SiGe HBTs. Depending on the bias and load condition, a significant fraction of electrons can be collected by the emitter rather than the collector. Most of the generated holes are collected by the substrate for deep ion strikes, and by the base for shallow ion strikes. A higher substrate doping can worsen the upset of the circuit function, despite the reduced total amount of charge collected. A lower substrate doping and a lower collector-substrate junction reverse bias are desired to improve SEU hardness.

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Section: Simulation Of See-induced Charge Collection In Uhv/cvd Sige mentioning

confidence: 99%

Simulation of SEE-induced charge collection in UHV/CVD SiGe HBTs

Niu¹,

Cressler²,

Shoga

et al. 2000

IEEE Trans. Nucl. Sci.

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“…The p-type substrate and the n-p-n layers of the intrinsic transistor form a n-p-n-p multilayer structure, complicating the charge collection process during ion strikes. This SiGe HBT technology features a peak of 50 GHz and a peak of 70 GHz [4]. The p-type substrate is biased at the lowest potential ( V and V in this case) for isolation.…”

Section: Device Technologymentioning

confidence: 99%

An SEU hardening approach for high-speed SiGe HBT digital logic

Krithivasan

Niu

Cressler

et al. 2003

IEEE Trans. Nucl. Sci.

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Abstract-A new circuit-level single-event upset (SEU) hardening approach for high-speed SiGe HBT current-steering digital logic is introduced and analyzed using both device and circuit simulations. The workhorse D-type flip-flop circuit architecture is modified in order to significantly improve its SEU immunity. Partial elimination of the effect of cross-coupling at the transistor level in the storage cell of this new circuit decreases its vulnerability to SEU. The SEU response of this new circuit is quantitatively compared with three other D flip-flop architectures, including the unhardened circuit, a conventional NAND gate based circuit, and a current-sharing hardened (CSH) circuit, at both variable data rate and switching current. The new circuit shows substantial improvement in SEU response over the unhardened version, with little increase in layout complexity and power consumption. While the NAND gate based circuit still shows better SEU response than the other circuits, its high power consumption will preclude its use in space applications. Our results suggest that this new circuit architecture exhibits sufficient SEU tolerance, low layout complexity, and modest power consumption, and thus should prove suitable for many space applications requiring very high-speed digital logic.

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“…The n-channel MOSFET's used in this experiment are from IBM's 0.35-m LDD BiCMOS technology [10], and have an 8-nm gate oxide, an n polysilicon gate, and rounded- The devices were measured on-wafer using a probe station capable of operating from 80 to 300 K. An array of devices with channel length ranging from 0.35 to 10 m were measured from 300 to 100 K in a spacing of 50 K. Fig. 1 shows the typical temperature sensitivity of the -characteristics for a 10-m wide and 0.55-m long n-channel device.…”

Section: Resultsmentioning

confidence: 99%

Enhanced low-temperature corner current-carrying inherent to shallow trench isolation (STI)

Niu

Cressler²,

Mathew³

et al. 1999

IEEE Electron Device Lett.

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The subthreshold hump in the current-voltage (I0V ) characteristics caused by the current-carrying corner in shallow-trench-isolated (STI) n-channel MOSFET's is significantly enhanced at reduced temperatures. Numerical simulations show that the sensitivity of the corner channel's threshold voltage to temperature is smaller than that of the center channel's threshold voltage. This, together with the reduced subthreshold swing at low temperatures, contribute to an enhanced subthreshold hump, and is potentially important for emerging cryogenic applications.

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Manufacturability demonstration of an integrated SiGe HBT technology for the analog and wireless marketplace

Cited by 80 publications

References 5 publications

Simulation of SEE-induced charge collection in UHV/CVD SiGe HBTs

Simulation of SEE-induced charge collection in UHV/CVD SiGe HBTs

An SEU hardening approach for high-speed SiGe HBT digital logic

Enhanced low-temperature corner current-carrying inherent to shallow trench isolation (STI)

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