Manufacturing pathway and experimental demonstration for nanoscale fine-grained 3-D integrated circuit fabric

Abstract

At Sub-20nm technologies CMOS scaling faces severe challenges primarily due to fundamental device scaling limitations, interconnection overhead and complex manufacturing. Migration to 3-D has been long sought as a possible pathway to continue scaling; however, CMOS's intrinsic requirements are not compatible for fine-grained 3-D integration. In [1], we proposed a truly fine-grained 3-D integrated circuit fabric called Skybridge that solves nanoscale challenges and achieves orders of magnitude benefits over CMOS. In Skybridge, device, circuit, connectivity, thermal management and manufacturing issues are addressed in an integrated 3-D compatible manner. At the core of Skybridge's assembly are uniform vertical nanowires, which are functionalized with architected features for fabric integration. All active components are created primarily using sequential material deposition steps on these nanowires. Lithography and doping are performed prior to any functionalization and their precision requirements are significantly reduced. This paper introduces Skybridge's manufacturing pathway that is developed based on extensive process, device simulations and experimental metrology, and uses established processes. Experimental demonstrations of key process steps are also shown.

Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling

“…Structure has to be firm and stable in order to apply gate voltage properly. Gate-all-around, monolithic 3D [14], and fine grained vertical 3D [15] like structures may be employed for enabling dense wiring. These are planned for both fabrication and simulation runs for comparison.…”

Power-delivery network in 3D ICs: Monolithic 3D vs. Skybridge 3D CMOS

“…Coaxial routing is enabled by specially configured material structures for insulating oxide and contact metal. Proper materials are chosen and deposited around nanowires to form low-resistivity interconnection between the silicon and the metallic bridge; Details of the contact structure and resistance evaluation are presented in [10].…”

“…Skybridge [7] is a truly fine-grained 3D IC fabric that uses vertically-stacked gates interconnected in 3D on a template of vertical nanowires to yield orders of magnitude benefits over 2D CMOS. Core fabric aspects including device, circuit-style, connectivity [8], thermal management [9] and pathway of manufacturing [10] are co-architected for 3D compatibility. Input/output pins for each vertically-composed gate have multiple points of access both horizontally and vertically which can be reached through architected routing components, as opposed to T-MI which limits pin-access to a 2D plane and relies on conventional routing schemes.…”