Many-Tier Vertical GAAFET (V-FET) for Ultra-Miniaturized Standard Cell Designs Beyond 5 nm

Abstract

The GAAFET (gate-all-around FET) is expected to replace FinFETs in future nodes due to its excellent channel controllability. It is also expected to be an impressive device due to its horizontal or vertical transistor structures. Vertical GAAFETs (V-FETs) are expected to be a promising device compared to horizontal GAAFETs (H-FETs) due to their structure, which allows area reduction and significant parasitic reduction. Besides, V-FETs are positioned on top of each other and thus allow more significant size reductions. Therefore, this paper studies the overall potential of many-tier V-FETs by investigating the essential design factors from the layout perspective. First, we study the factors that should be considered for designing many-tier V-FETs. Second, we propose an interconnect structure that maximizes the advantages of many-tier V-FETs. Third, we compare 2-tier V-FET standard cells to one-tier V-FET cells and visualize the advantages that many-tier V-FET cells provide. Our study shows that 2-tier V-FET standard cells provide a-35.6% area reduction with a cost of +16.5% wirelength and +13.2% parasitic capacitance increase compared to 1-tier V-FET cells. Compared to H-FETs and FinFETs, our cells show-50.1% area reductions with-0.3% wirelength reductions and-18.9% parasitic capacitance reductions. We emphasize that the design freedom to place transistors on top of each other and proper interconnect structures lead to ultra-scale miniaturized standard cell designs. We note that the increase in wirelength and capacitance is due to the vertical size increases and detours that must exist in the designs. Thus, careful circuit design is required to obtain the maximum advantages from V-FETs.

Many-Tier Vertical Gate-All-Around Nanowire FET Standard Cell Synthesis for Advanced Technology Nodes

“…Inspired by [25], we adopt the assumptions on the interconnect structure for many-tier VFETs as illustrated in Fig. 2(a).…”

“…Our framework considers 5nm standard cell architecture (e.g., layer/track information) of [25], as depicted in Fig. 3.…”

“…In [23], the authors have presented area and routing optimization strategies. Furthermore, recent literatures [24], [25] describe a guideline with an interconnect structure to harvest the maximum advantages of 1-tier as well as many-tier VFETs which stack multiple transistors on the same transistor footprint. They also show that 2-tier VFET SDCs provide a 36.5% reduction of the cell area compared to 1-tier VFET SDCs.…”

“…• We compare the optimized cell area by using our concurrent P&R approach over the previous work [25]. • We explore the substantial gain of many-tier VFET configurations up to 4 tiers on the cell-level metrics and block-level areas, throughout the various experiments.…”

Growth and Selective Etch of Phosphorus-Doped Silicon/Silicon–Germanium Multilayers Structures for Vertical Transistors Application

“…Lateral and vertical nanowires/nanosheets are main structures according to International Roadmap for Device and Systems (IRDS) 2020 to replace FinFETs [ 7 ]. Vertical GAAFETs (or vGAAFETs) have free flexibility design on gate length and have great potential to increase integrated density [ 4 , 8 ]. There are two main categories to implement vertical nanowire structures: bottom-up and top-down.…”