Mapping algorithms to VLSI array processors

Experiment Design Regularization-Based Hardware/Software Codesign for Real-Time Enhanced Imaging in Uncertain Remote Sensing Environment

“…Because of the extremely high dimension ( 12 of the operator inversions required to form the corresponding SOs specified by (20), (21), it is questionable to recommend the general-form DEDRoptimal method (22) as a practical enhanced RS imaging technique realizable in (near) real computational time.…”

“…In this section, we proceed with the development of the procedure for mapping the corresponding algorithms onto array processors. A systolic array consists of a number of processor elements (PEs) with the corresponding interconnection links among the PEs, and the mapping technique transforms a space representation into a space-time representation [21]. Systolic arrays are being used for matrix operations and required specific processing algorithms, such as, transform techniques, matrix multiplication, convolution, and so forth, [21,22] of mapping the algorithms onto array structures is depicted in Figure 5.…”

“…A systolic array consists of a number of processor elements (PEs) with the corresponding interconnection links among the PEs, and the mapping technique transforms a space representation into a space-time representation [21]. Systolic arrays are being used for matrix operations and required specific processing algorithms, such as, transform techniques, matrix multiplication, convolution, and so forth, [21,22] of mapping the algorithms onto array structures is depicted in Figure 5. First, to achieve the desired maximal possible parallelism in an algorithm, we perform the analysis of the data dependencies in the corresponding computations.…”

Near Real Time Enhancement of Remote Sensing Imagery Based on a Network of Systolic Arrays

“…Now, we are ready to proceed with the algorithms transformation into their locally recursive format representation [10], in which the data dependencies of the computations are exposed in a dependence graphs (DG) [11] to represent the parallel characteristics of the algorithms.…”

“…In order to derive a regular SA architecture with a minimum possible number of nodes, we employ a linear projection approach for processor assignment, i.e., the nodes of the DG in a certain straight line are projected onto the corresponding PEs in the processor array represented by the corresponding assignment projection vector d . Thus, we seek for a linear order reduction transformation T [10] where…”