Mapping Arbitrary Logic Functions onto Carry Chains in FPGAs

Senhadji-Navarro, Raouf; García-Vargas, Ignacio

doi:10.3390/electronics11010027

Cited by 8 publications

(11 citation statements)

References 20 publications

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“…A very recent publication also attempts to map a general logic equation into an FPGA [17]. Its methodology creates AND and OR equations which are similar to AND and OR equations used in this work.…”

Section: Carry Chain Lbmentioning

confidence: 99%

“…6 implements an OR equation, but not the same type of OR equation used in [17]. The [17] OR equation has a default of 0, and a segment true OR result writes a 1 to the CO output. In Fig.…”

Section: N-sorters Using Carry Chain Logicmentioning

confidence: 99%

“…The Fig. 8 equations are OR equations that are implemented in essentially the same manner as the OR equations in [17]. The equation default is 0, and any true product term result will cause a DI 1 to be written to CO.…”

Section: N-sorters Using Carry Chain Logicmentioning

confidence: 99%

“…Each segment DI input is a 0, which is written to the chain whenever a segment equation fails. This is the same type of AND equation used in [17].…”

Section: A N-max/n-min Filters Using Carry Chain Logicmentioning

confidence: 99%

“…A number of researchers have published applications which use FPGA carry chain logic, but most of these carry chain logic uses are not closely related to the way this logic is used in this study [8]- [16]. A very recent publication [17] does use carry chain logic in a manner similar to some of the ways used here for N-sorter/N-filter design, but none of these publications target using carry chain logic for sorting devices.…”

mentioning

confidence: 99%

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Use of Carry Chain Logic and Design System Extensions to Construct Significantly Faster and Larger Single-Stage N-Sorters and N-Filters

Kent

Pattichis

2022

IEEE Access

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The authors' recently published design system for the creation of single-stage N-sorter/N-filter sorting devices, which were implemented using a particular example hardware block, is here expanded and applied to a second hardware type, FPGA carry chain logic. Although several researchers have published applications which use FPGA carry chain logic, most do not use carry chain logic as is done here, and none of the applications target sorting devices. Prior to the introduction of the single-stage N-sorter/N-filter design system, the fastest state-of-the-art hardware devices which sorted more than 2 input values were multistage sorting networks, in which the sorting process is performed by one or more 2-sorters and 2-max/2-min filters, operating in each sequential stage. Using the authors' original design system, single-stage N-sorters and N-filters were shown to be faster than the fastest comparable sorting networks when sorting 3 to 9 inputs. Here, product term splitting and a new Sum-of-Products output multiplexer equation are added to the design system, and this expanded design system is then implemented in carry chain logic to build faster and larger N-sorters, and much larger and still fast N-max/N-min filters. The new carry chain N-sorters are implemented in the FPGA used in the Amazon AWS EC2 F1 instance, which is one of the two example FPGAs utilized in the previous publication. A carry chain logic 16-sorter, not practical when using the original hardware block, has a speedup of 4.61 relative to the fastest 16-network. An example of the new, very large single-stage carry chain N-max filters is the 125-max 5x5x5 CNN video max pooling filter, which operates in only 2.075 nS. A 2-stage 1024-max network, using single-stage 32-max carry chain filters, has a speedup of 2.85 versus the existing state-of-the-art 10-stage network of 2-max filters.

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Section: Carry Chain Lbmentioning

confidence: 99%

“…6 implements an OR equation, but not the same type of OR equation used in [17]. The [17] OR equation has a default of 0, and a segment true OR result writes a 1 to the CO output. In Fig.…”

Section: N-sorters Using Carry Chain Logicmentioning

confidence: 99%

Section: N-sorters Using Carry Chain Logicmentioning

confidence: 99%

“…Each segment DI input is a 0, which is written to the chain whenever a segment equation fails. This is the same type of AND equation used in [17].…”

Section: A N-max/n-min Filters Using Carry Chain Logicmentioning

confidence: 99%

mentioning

confidence: 99%

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Use of Carry Chain Logic and Design System Extensions to Construct Significantly Faster and Larger Single-Stage N-Sorters and N-Filters

Kent

Pattichis

2022

IEEE Access

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Hardware Reduction for FSMs With Extended State Codes

Barkalov,

Titarenko,

Mielcarek

et al. 2024

IEEE Access

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A method is proposed for reducing chip area occupied by logic circuits of FPGAbased Mealy finite state machines (FSMs). The proposed method aims at optimization of FSM circuits implemented with look-up table (LUT) elements of FPGA chip. The proposed method combines positive features of such state assignment methods as extended (ESCs) and composite (CSCs) state codes. The method is based on finding a partition of the set of internal states by classes of compatible states. To reduce LUT count, we propose a special kind of states codes named mixed state codes. These codes include two parts. The first part includes the maximum binary codes of states as elements of some partition class. The second part consists of the code of corresponding partition class. Unlike CSCs, the proposed approach allows obtaining partial state codes having different lengths. Unlike ESCs, all partial state codes consist of the same variables. Using mixed state codes allows obtaining LUT-based FSM circuits with exactly two levels of logic. The first level generates partial Boolean functions. The second level combines them into FSM outputs and input memory functions. If some conditions hold, then both levels consist of single-LUT circuits. Example of FSM synthesis based on mixed state codes is shown. The conducted experiments prove that the proposed approach allows reducing hardware compared with FSMs based on JEDI, one-hot state codes, CSCs and ESCs. On average, the proposed method reduces the value of LUT count by 6.21% compared to CSC-based FSMs and 22.21% compared to ESC-based counterparts. The advantages of the proposed approach grow with the growth of FSM complexness. An additional positive effect of the proposed method is a slight increase in the operating frequency.INDEX TERMS Mealy FSM, FPGA, LUT count, synthesis, extended state codes, composite state codes, mixed state codes.

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Improving Hardware in LUT-Based Mealy FSMs

2022

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The main contribution of this paper is a novel design method reducing the number of look-up table (LUT) elements in the circuits of three-block Mealy finite-state machines (FSMs). The proposed method is based on using codes of collections of outputs (COs) for representing both FSM state variables and outputs. The interstate transitions are represented by output collections generated during two adjacent cycles of FSM operation. To avoid doubling the number of variables encoding of COs, two registers are used. The first register keeps a code of CO produced in the current cycle of operation; the code of a CO produced in the previous cycle is kept in the second register. There is given a synthesis example with applying the proposed method. The results of the research are shown. The research is conducted using the CAD tool Vivado by Xilinx. The experiments prove that the proposed approach allows reducing the hardware compared with such known methods as auto and one-hot of Vivado, and JEDI. Additionally, the proposed approach gives better results than a method based on the simultaneous replacement of inputs and encoding of COs. Compared to circuits of the three-block FSMs, the LUT counts are reduced by an average of 7.21% without significant reduction in the performance. Our approach loses in terms of power consumption (on average 9.62%) and power–time products (on average 10.44%). The gain in LUT counts and area–time products increases with the increase in the numbers of FSM states and inputs.

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Mapping Arbitrary Logic Functions onto Carry Chains in FPGAs

Cited by 8 publications

References 20 publications

Use of Carry Chain Logic and Design System Extensions to Construct Significantly Faster and Larger Single-Stage N-Sorters and N-Filters

Use of Carry Chain Logic and Design System Extensions to Construct Significantly Faster and Larger Single-Stage N-Sorters and N-Filters

Hardware Reduction for FSMs With Extended State Codes

Improving Hardware in LUT-Based Mealy FSMs

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