Mapping into LUT structures

Ray,; Mishchenko,; Een,; Jang,; Chen, Guihai

doi:10.1109/date.2012.6176724

Cited by 25 publications

(19 citation statements)

References 12 publications

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“…The proposed algorithm is on average faster than [8] and computes fewer classes. Another difference is that the proposed algorithm scales to functions up to 16 inputs, which is important for practical applications, such as mapping into LUT structures [12] and technology-independent synthesis [13].…”

Section: B Comparing With Previous Workmentioning

confidence: 99%

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Fast Boolean matching based on NPN classification

Huang

Wang

Nasikovskiy

et al. 2013

2013 International Conference on Field-Programmable Technology (FPT)

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Abstract-This paper proposes a fast algorithm for Boolean matching of completely specified Boolean functions. The algorithm is based on the NPN classification and can be applied on-the-fly to millions of small practical functions appearing in industrial designs, leading to runtime and memory reduction in logic synthesis and technology mapping. The algorithm is conceptually simpler, faster, and more scalable than previous work. I. IntroductionAn NPN class is a set of Boolean functions derived from each other by permuting and complementing the inputs, and complementing the output. Boolean matching determines whether two Boolean functions belong to the same NPN class. In the practical applications, Boolean matching is used to match a function against a library of functions whose implementation or other properties are known or have been pre-computed.AIG This paper presents two algorithms: a fast heuristic one and a slower nearly-exact one. They are compared against [8] believed to be state-of-the-art in Boolean matching on a large set of small practical functions derived from industrial designs. The conclusion is that the proposed heuristic algorithm is often faster without degrading quality, while a more elaborate nearly-exact algorithm computes fewer classes than [8]. Moreover, [8] cannot be applied to functions of more than 9 inputs, which limits its practicality. Meanwhile, the proposed algorithm scales to 16 variables and is therefore a better fit for cut-based logic synthesis and technology mapping.The rest of the paper is organized as follows: Section II contains relevant background. Section III describes the proposed three-step algorithm. Section IV shows experimental results. Section V concludes the paper.

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Section: B Comparing With Previous Workmentioning

confidence: 99%

“…• Use the algorithm to enhance mapping into both standard cells [6] and LUT structures [12]. Indeed, matches for each function can be precomputed and saved for each semicanonical class, resulting in reduced runtime.…”

Section: B Comparing With Previous Workmentioning

confidence: 99%

Fast Boolean matching based on NPN classification

Huang

Wang

Nasikovskiy

et al. 2013

2013 International Conference on Field-Programmable Technology (FPT)

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“…For example, LUT structures combine two or more LUTs in one cell [5] [17]. Other extensions include cells based on LUTs and AND gates [1], LUTs and MUXes [4] [16], and cones of elementary gates [20].…”

Section: Introductionmentioning

confidence: 98%

Technology Mapping into General Programmable Cells

Mishchenko

Brayton

et al. 2015

Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

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Field-Programmable Gate Arrays (FPGA) implement logic functions using programmable cells, such as K-input lookuptables (K-LUTs). A K-LUT can implement any Boolean function with K inputs and one output. Methods for mapping into K-LUTs are extensively researched and widely used. Recently, cells other than K-LUTs have been explored, for example, those composed of several LUTs and those combining LUTs with several gates. Known methods for mapping into these cells are specialized and complicated, requiring a substantial effort to evaluate custom cell architectures. This paper presents a general approach to efficiently map into single-output K-input cells containing LUTs, MUXes, and other elementary gates. Cells with to 16 inputs can be handled. The mapper is fully automated and takes a logic network and a symbolic description of a programmable cell, and produces an optimized network composed of instances of the given cell. Past work on delay/area optimization during mapping is applicable and leads to good quality of results.

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“…A method for caching decomposable functions to up 16 inputs is used in [25] to speed up FPGA mapping. Both approaches precompute logic structures in terms of LUTs, rather than AIGs, as in the present work.…”

Section: Previous Workmentioning

confidence: 99%

Lazy man's logic synthesis

Yang

Wang

Mishchenko

2012

Proceedings of the International Conference on Computer-Aided Design

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Abstract-Deriving a circuit for a Boolean function or improving an available circuit are typical tasks solved by logic synthesis. Numerous algorithms in this area have been proposed and implemented over the last 50 years. This paper presents a "lazy" approach to logic synthesis based on the following observations: (a) optimal or near-optimal circuits for many practical functions are already derived by the tools, making it unnecessary to implement new algorithms or even run the old ones repeatedly; (b) larger circuits are composed of smaller ones, which are often isomorphic up to a permutation/negation of inputs/outputs. Experiments confirm these observations. Moreover, a case-study shows that logic level minimization using lazy man's synthesis improves delay after LUT mapping into 4-and 6-input LUTs, compared to earlier work on high-effort delay optimization.

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Mapping into LUT structures

Abstract: Mapping into K-input lookup tables (K-LUTs

Cited by 25 publications

References 12 publications

Fast Boolean matching based on NPN classification

Fast Boolean matching based on NPN classification

Technology Mapping into General Programmable Cells

Lazy man's logic synthesis

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