Mapping Multiple LSTM models on FPGAs

Ribes, Stefano; Trancoso, Pedro; Sourdis, Ioannis; Bouganis, Christos-Savvas

doi:10.1109/icfpt51103.2020.00010

Cited by 8 publications

(5 citation statements)

References 24 publications

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“…Following [37], we conduct a design space exploration to find a parameter set that gives the best performance under FPGA resource and bandwidth constraints. Due to page limit, we briefly describe the performance model for each module, which is defined as:…”

Section: Design Space Exploration For P3netcorementioning

confidence: 99%

An Integrated FPGA Accelerator for Deep Learning-Based 2D/3D Path Planning

Sugiura,

Matsutani

2024

IEEE Trans. Comput.

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Path planning is a crucial component for realizing the autonomy of mobile robots. However, due to limited computational resources on mobile robots, it remains challenging to deploy state-of-the-art methods and achieve real-time performance. To address this, we propose P3Net (PointNet-based Path Planning Networks), a lightweight deep-learning-based method for 2D/3D path planning, and design an IP core (P3NetCore) targeting FPGA SoCs (Xilinx ZCU104). P3Net improves the algorithm and model architecture of the recently-proposed MPNet. P3Net employs an encoder with a PointNet backbone and a lightweight planning network in order to extract robust point cloud features and sample path points from a promising region. P3NetCore is comprised of the fully-pipelined point cloud encoder, batched bidirectional path planner, and parallel collision checker, to cover most part of the algorithm. On the 2D (3D) datasets, P3Net with the IP core runs 30. 52-186.36x and 7.68-143.62x (15.69-93.26x and 5.30-45.27x) faster than ARM Cortex CPU and Nvidia Jetson while only consuming 0.255W (0.809W), and is up to 1278.14x (455.34x) power-efficient than the workstation. P3Net improves the success rate by up to 28.2% and plans a near-optimal path, leading to a significantly better tradeoff between computation and solution quality than MPNet and the state-of-the-art sampling-based methods.

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Section: Design Space Exploration For P3netcorementioning

confidence: 99%

An Integrated FPGA Accelerator for Deep Learning-Based 2D/3D Path Planning

Sugiura,

Matsutani

2024

IEEE Trans. Comput.

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“…Authors of [6,24] have shown that deeper networks are more resilient, and the use of batch normalization layers in the neural network architecture helps in generalizing and improving the resiliency of the network model. In [34] was figured that, that the impact of fault is more when it happens at the back of the network (i.e., in the last layers), whereas faults effects tend to be mitigated or neutralized if happening in the initial layers of the network ( i.e., the first layer). In [6,27] was demonstrated that pruning and quantization also assist in increasing the resiliency of the network model.…”

Section: Factors Affecting the Resiliency Of Deep Neural Networkmentioning

confidence: 99%

A Survey on Fault-Tolerant Methodologies for Deep Neural Networks

Syed¹,

Ulbricht²,

Piotrowski³

et al. 2023

PAR

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Asignificant rise in Artificial Intelligence (AI) has impacted many applications around us, so much so that AI has now been increasingly used in safety-critical applications. AI at the edge is the reality, which means performing the data computation closer to the source of the data, as opposed to performing it on the cloud. Safety-critical applications have strict reliability requirements; therefore, it is essential that AI models running on the edge (i.e., hardware) must fulfill the required safety standards. In the vast field of AI, Deep Neural Networks (DNNs) are the focal point of this survey as it has continued to produce extraordinary outcomes in various applications i.e. medical, automotive, aerospace, defense, etc. Traditional reliability techniques for DNNs implementation are not always practical, as they fail to exploit the unique characteristics of the DNNs. Furthermore, it is also essential to understand the targeted edge hardware because the impact of the faults can be different in ASICs and FPGAs. Therefore, in this survey, first, we have examined the impact of the fault in ASICs and FPGAs, and then we seek to provide a glimpse of the recent progress made towards the fault-tolerant DNNs. We have discussed several factors that can impact the reliability of the DNNs. Further, we have extended this discussion to shed light on many state-of-the-art fault mitigation techniques for DNNs.

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“…An early approach in this direction was presented in [13] in the context of multi-LSTM applications. The proposed scheme tunably decomposes the weight matrices of multiple LSTM models and represents them with a shared lowrank representation.…”

Section: Approximate Computing For Multiple Dnnsmentioning

confidence: 99%

Multi-DNN Accelerators for Next-Generation AI Systems

Venieris¹,

Bouganis²,

Lane³

2022

Preprint

Self Cite

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As the use of AI-powered applications widens across multiple domains, so do increase the computational demands. Primary driver of AI technology are the deep neural networks (DNNs). When focusing either on cloud-based systems that serve multiple AI queries from different users each with their own DNN model, or on mobile robots and smartphones employing pipelines of various models or parallel DNNs for the concurrent processing of multi-modal data, the next generation of AI systems will have multi-DNN workloads at their core. Large-scale deployment of AI services and integration across mobile and embedded systems require additional breakthroughs in the computer architecture front, with processors that can maintain high performance as the number of DNNs increases while meeting the quality-of-service requirements, giving rise to the topic of multi-DNN accelerator design.

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Mapping Multiple LSTM models on FPGAs

Cited by 8 publications

References 24 publications

An Integrated FPGA Accelerator for Deep Learning-Based 2D/3D Path Planning

An Integrated FPGA Accelerator for Deep Learning-Based 2D/3D Path Planning

A Survey on Fault-Tolerant Methodologies for Deep Neural Networks

Multi-DNN Accelerators for Next-Generation AI Systems

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