Mapping multirate dataflow to complex RT level hardware models

Horstmannshoff, Jens; Grotker, T.; Meyr, H.

doi:10.1109/asap.1997.606834

Cited by 17 publications

(18 citation statements)

References 7 publications

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“…For hardware synthesis, a similar approach can be taken, with blocks implementing their functionality in a hardware description language, like behavioral VHSIC hardware descripton language (VHDL) [12], [34]. The generated VHDL description can then be used by a behavioral synthesis tools to generate a register transfer level (RTL) description of the system that can be further compiled into hardware using logic synthesis and layout tools.…”

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confidence: 99%

Shared buffer implementations of signal processing systems using lifetime analysis techniques

Murthy¹,

Bhattacharyya

2001

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-There has been a proliferation of block-diagram environments for specifying and prototyping digital signal processing (DSP) systems. These include tools from academia such as Ptolemy and commercial tools such as DSPCanvas from Angeles Design Systems, signal processing work system (SPW) from Cadence, and COSSAP from Synopsys. The block diagram languages used in these environments are usually based on dataflow semantics because various subsets of dataflow have proven to be good matches for expressing and modeling signal processing systems. In particular, synchronous dataflow (SDF) has been found to be a particularly good match for expressing multirate signal processing systems. One of the key problems that arises during synthesis from an SDF specification is scheduling. Past work on scheduling from SDF has focused on optimization of program memory and buffer memory under a model that did not exploit sharing opportunities. In this paper, we build on our previously developed analysis and optimization framework for looped schedules to formally tackle the problem of generating optimally compact schedules for SDF graphs. We develop techniques for computing these optimally compact schedules in a manner that also attempt to minimize buffering memory under the assumption that buffers will be shared. This results in schedules whose data memory usage is drastically lower than methods in the past have achieved. The method we use is that of lifetime analysis; we develop a model for buffer lifetimes in SDF graphs and develop scheduling algorithms that attempt to generate schedules that minimize the maximum number of live tokens under the particular buffer lifetime model. We develop several efficient algorithms for extracting the relevant lifetimes from the SDF schedule. We then use the well-known firstfit heuristic for packing arrays efficiently into memory. We report extensive experimental results on applying these techniques to several practical SDF systems and show improvements that average 50% over previous techniques, with some systems exhibiting up to an 83% improvement over previous techniques.

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confidence: 99%

Shared buffer implementations of signal processing systems using lifetime analysis techniques

Murthy¹,

Bhattacharyya

2001

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…But this hardware overhead is much smaller than that of parallel implementation. One difficulty of this approach is to generate numerous control signals whose timings are computed statically through rigorous graph analysis [8]. Another limitation is that all hardware blocks should have deterministic and fixed execution cycles for static timing analysis and controller synthesis.…”

Section: Previous Work and Motivational Examplementioning

confidence: 99%

Hardware synthesis from coarse-grained dataflow specification for fast HW/SW cosynthesis

Jung

2004

Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis - CODES+ISSS

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This paper concerns automatic hardware synthesis from data flow graph (DFG) specification for fast HW/SW cosynthesis. A node in DFG represents a coarse grain block such as FIR and DCT and a port in a block may consume multiple data samples per invocation, which distinguishes our approach from behavioral synthesis and complicates the problem. In the presented design methodology, a dataflow graph with specified algorithm can be mapped to various hardware structures according to the resource allocation and schedule information. This simplifies the management of the area/performance tradeoff in hardware design and widens the design space of hardware implementation of a dataflow graph compared with the previous approaches. Through experiments with some examples, the usefulness of the proposed technique is demonstrated.

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“…Synchronous reactive systems [5] and cyclostatic dataflow (CSDF) [6] provide more of a front-end view of the problem: They deal with logical modeling of the timing and are more concerned with verifying the functionality. The RT-level model proposed in [3] provides an interesting approach to the problem of multirate timing and interfacing but requires a master clock that is potentially much faster than any of the data rates in the system in order to synchronize the interfaces. Models such as the processor timing data used in [7] capture the effects of real system parameters and latency for single rate systems, but they do not provide ways to take advantage of skewed clock phases or multirate graphs directly.…”

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confidence: 99%

The hierarchical timing pair model for multirate DSP applications

Chandrachoodan

Bhattacharyya

Liu

2004

IEEE Trans. Signal Process.

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Abstract-The problem of representing timing information associated with functions in a dataflow graph is considered. This information is used for constraint analysis during behavioral synthesis of appropriate architectures for implementing the graph. Conventional models for timing suffer from shortcomings that make it difficult to represent timing information in a hierarchical manner for sequential and multirate systems. Some of these shortcomings are identified, and an alternate timing model that does not have these problems for hardware implementations is provided.We introduce the concept of timing pairs to model delay elements in sequential and multirate circuits and show how this allows us to derive hierarchical timing information for complex circuits. The resulting compact representation of the timing information can be used to streamline system performance analysis. In addition, several analytical results that previously applied only to single rate systems can now be extended to multirate systems.We present an algorithm to compute the timing parameters and have used this to compute timing parameters for a number of benchmark circuits. The results obtained on several ISCAS benchmark circuits as well as several multirate dataflow graphs corresponding to useful signal processing applications are presented. These results show that the new representation model can result in large reductions in the amount of information required to represent timing for hierarchical systems.

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Mapping multirate dataflow to complex RT level hardware models

Cited by 17 publications

References 7 publications

Shared buffer implementations of signal processing systems using lifetime analysis techniques

Shared buffer implementations of signal processing systems using lifetime analysis techniques

Hardware synthesis from coarse-grained dataflow specification for fast HW/SW cosynthesis

The hierarchical timing pair model for multirate DSP applications

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