2008 IEEE/ACS International Conference on Computer Systems and Applications 2008
DOI: 10.1109/aiccsa.2008.4493576
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Mapping task graphs onto Network Processors using genetic algorithm

Abstract: Network Processors (NPs) are embedded system-on-achip multiprocessors that are optimized to perform simple packet processing tasks at data rates of several Gigabytes per second. They are the key components to build a performance-scalable and function-flexible network systems. To meet the performance demands of increasing link speeds and more complex network applications, NPs are implemented with several dozen of processor cores and run multiple packet processing applications in parallel. This trend makes it in… Show more

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Cited by 5 publications
(1 citation statement)
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“…Various techniques for task mapping in conventional wired Network-on-Chip have been discussed in prior research papers [11][12][13][14][15][16][17][18][19]. Static mapping techniques for conventional wired NoC have been covered in [13] and [15] while [12] and [11] introduce two genetic mapping approaches. However, these methods are not well-suited for real-time applications that are subject to constraints and deadlines.…”
Section: Related Workmentioning
confidence: 99%
“…Various techniques for task mapping in conventional wired Network-on-Chip have been discussed in prior research papers [11][12][13][14][15][16][17][18][19]. Static mapping techniques for conventional wired NoC have been covered in [13] and [15] while [12] and [11] introduce two genetic mapping approaches. However, these methods are not well-suited for real-time applications that are subject to constraints and deadlines.…”
Section: Related Workmentioning
confidence: 99%