Mapping the FDTD Application to Many-Core Chip Architectures

Abstract

Abstract-This paper reports a study of mapping the Finite Difference Time Domain (FDTD) application to the IBM Cyclops-64 (C64) many-core chip architecture [1]. C64 is chosen for this study as it represents the current trend in computer architecture to develop a class of many-core architectures with distinct features e.g. software manageable on-chip memory hierarchy (vs. a hardware-managed data cache), high on-chip bandwidth, fine grain multithreading and synchronization, among others.Major results of our study include: 1. A good mapping of FDTD can effectively exploit the on-chip parallelism of C64-like architectures and show good performance and scalability.2. Such performance improvement is derived by employing a number of code optimization techniques such as time skewing and split tiling that judiciously exploit the architecture features described in (1).3. High performance requires maximum reuse of on-chip memory, which is obtained by tiling with non conventional tile shapes.4. Such code optimization techniques we used in (2) and tiling such as the one used in (3) should be implementable within a reasonable compilation framework, opening a new set of possibilities for compiler optimizations.

Data Layout Transformation for Stencil Computations on Short-Vector SIMD Architectures

“…In addition, other transformations such as tiling of stencil computations for multicore architectures have been addressed in [43], [25], [21], [34]. Recently, memory customization for stencils has been proposed in [36].…”

“…FDTD 2D This kernel is the core computation in the widely used Finite Difference Time Domain method in Computational Electromagnetics [34] Rician Denoise 2D This application performs noise removal from MRI images and involves an iterative loop that performs a sequence of stencil operations.…”

TIDeFlow: The Time Iterated Dependency Flow Execution Model

“…Cyclops-64 has been described extensively in previous publications [10,16,5]. Cyclops-64 was chosen for our experiments because its large number of execution units allow excellent studies in scalability and parallelism for HPC programs.…”

Cache oblivious parallelograms in iterative stencil computations

“…In cache aware time skewing schemes, flat parallelization strategies are applied [11,12,18]. The cache sizes are known, so it is clear when it is better to parallelize the execution of the sub-tiles, forcing them into different caches, and when to leave them in the same cache for better data locality and process them sequentially with a single thread.…”