Mask characterization for double patterning lithography

Bubke, Karsten; Cotte, Eric; Peters, Jan Hendrik; Kruif, Robert de; Dusa, Mircea V.; Fochler, Joerg; Connolly, Brid

doi:10.1117/12.747006

Cited by 6 publications

(4 citation statements)

References 11 publications

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“…This was triggered by a former presentation [2] showing good correlation between reticle and wafer overlay data. In this presentation, it was concluded that improving mask registration would have a direct impact on wafer overlay performance.…”

Section: Feedforward Higher Order Field Correction Based On Lms Ipro4mentioning

confidence: 99%

Mask registration and wafer overlay

Lee¹,

Bang²,

Kim³

et al. 2010

SPIE Proceedings

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Overlay continues to be one of the key challenges for lithography in advanced semiconductor manufacturing. It becomes even more challenging due to the continued shrinking of the device node. Some low k1 techniques, such as Double Exposure and Double Patterning also add additional loss of the overlay margin due to the fact that the single layer pattern is created based on more than 1 exposure. Therefore, the overlay between 2 exposures requires very tight overlay specification.Mask registration is one of the major contributors to wafer overlay, especially field related overlay. We investigated mask registration and wafer overlay by co-analyzing the mask data and the wafer overlay data. To achieve the accurate cohesive results, we introduced the combined metrology mark which can be used for both mask registration measurement as well as for wafer overlay measurement. Coincidence of both metrology marks make it possible to subtract mask signature from wafer overlay without compromising the accuracy due to the physical distance between measurement marks, if we use 2 different marks for both metrologies. Therefore, it is possible to extract pure scanner related signatures, and to analyze the scanner related signatures in details to in order to enable root cause analysis and ultimately drive higher wafer yield. We determined the exact mask registration error in order to decompose wafer overlay into mask, scanner, process and metrology. We also studied the impact of pellicle mounting by comparison of mask registration measurement pre-pellicle mounting and post-pellicle mounting in this investigation.

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Section: Feedforward Higher Order Field Correction Based On Lms Ipro4mentioning

confidence: 99%

Mask registration and wafer overlay

Lee¹,

Bang²,

Kim³

et al. 2010

SPIE Proceedings

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show abstract

“…In DPL, registration error of the two exposures is observed to be correlated and, as a result, the impact on overlay is greatly reduced. This correlation is mainly attributed to mask-layout similarity [29,30]. In ST-DPL, registration error is expected to have a higher correlation factor than in the case of standard DPL since mask-layout is exactly the same for both exposures.…”

Section: A Overlay and Throughput Benefitsmentioning

confidence: 99%

Single-Mask Double-Patterning Lithography for Reduced Cost and Improved Overlay Control

Ghaida

Torres

Gupta

2011

IEEE Trans. Semicond. Manufact.

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Abstract-1 We propose shift-trim double patterning lithography (ST-DPL), a cost-effective double patterning technique for achieving pitch relaxation with a single photomask. The mask is re-used for the second exposure by applying a translational mask-shift. An additional non-critical trim exposure is applied to remove extra printed features. ST-DPL can be used to pattern critical layers and is very suitable for regular and gridded layouts, where redesign effort and area overhead are minimal. In this paper, the viability of ST-DPL is demonstrated through a design implementation at the poly and contacts layers in bidirectional layouts. Standard-cell layouts are constructed so as to avoid layout decomposition conflicts, which are found to be the limiting factor for the pitch relaxation that can be achieved with double-patterning (ST-DPL as well as standard DPL). 2× pitch relaxation being associated with a considerable area overhead, 1.8× pitch relaxation is achieved in our implementation while ensuring no layout decomposition conflicts and a small area overhead. Specifically, in comparison to layouts assumed to be feasible with a hypothetical single-patterning process, we observe virtually no area overhead when ST-DPL is applied to the poly layer (<0.3% cell-area overhead) and no more than 4.7% cellarea overhead when ST-DPL is applied at both the poly and contacts layers. The proposed method has many benefits over standard pitch-split double-patterning: (1) cuts mask-cost to nearly half, (2) reduces overlay errors between the two patterns, (3) alleviates the bimodal line-width distribution problem in double patterning, and (4) slightly enhances the throughput of critical-layer scanners.

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“…In DPL, registration error of the two exposures is observed to be correlated which greatly reduces its impact on overlay. This correlation is mainly attributed to mask-layout similarity [11,25]. In ST-DPL, registration error is expected to have a higher correlation factor than in the case of standard DPL since mask-layout is exactly the same for both exposures.…”

Section: Overlay and Throughput Benefitsmentioning

confidence: 99%

Single-mask double-patterning lithography

2009

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This paper proposes shift-trim double patterning lithography (ST-DPL), a cost-effective method for achieving 2× pitchrelaxation with a single photomask (especially at polysilicon layer). The mask is re-used for the second exposure by applying a translational mask-shift. Extra printed features are then removed using a non-critical trim exposure. The viability of ST-DPL is demonstrated. The proposed method has many advantages with virtually no area overhead (< 0.3% standard-cell area): (1) cuts mask-cost to nearly half that of standard-DPL, (2) reduces overlay errors between the two patterns and can virtually eliminate it in some process implementations, (3) alleviates the bimodal problem in doublepatterning, and (4) enhances throughput of first-rate scanners. We implement a small 45nm standard-cell library and small benchmark designs with ST-DPL to illustrate its viability.

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Mask characterization for double patterning lithography

Cited by 6 publications

References 11 publications

Mask registration and wafer overlay

Mask registration and wafer overlay

Single-Mask Double-Patterning Lithography for Reduced Cost and Improved Overlay Control

Single-mask double-patterning lithography

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