Mask cost and cycle time reduction

Abstract

In the IC industry the mask cost and cycle time have increased dramatically since the chip design has become more complex and the required mask specification, tighter. The lithography technology has been driven to 65-nm node and 90-nm product will be manufacturing in 2004, according to ITRS's roadmap. However, the optical exposure tools do not extend to a shorter wavelength as the critical dimension (CD) shrinks. In such sub-wavelength technology generation, the mask error factor (MEF) is normally higher. Higher MEF means that tighter mask specification is required to sustain the lithography performance. The tighter mask specification will impact both mask processing complexity and cost. The mask is no longer a low-cost process. In addition, the number of wafers printed from each mask set is trending down, resulting in a huge investment to tape out a new circuit. Higher cost discourages circuit shrinking, thus, prohibits commercialization of new technology nodes.How to reduce the mask cost and cycle time? Robust mask processes will play a crucial role but it is an extreme challenge for the mask-processing people. For example, the blank mask provided by the vender has been coated with the resist. Each batch of blank masks needs to find an optimal dose to meet the rigorous CD specification, since these coating blanks are sent out to the mask house in different periods and through different transportation conditions. The cycle time and the data size also increase drastically when higher transistor density is demanded and smaller pattern jags are created by the aggressive OPC. The vacuum, heating and fogging effects will worsen the process control of the e-beam writer due to a long writing time. The well-controlled transmission and phase shift changes after the cleaning process also become crucial, when an Att-PSM consisting of lines and spaces is fabricated. Dry cleaning may be one possible solution. The mask cost contributed from the defect inspection process has risen significantly, since the price of next generation tool increased but the throughput decreased. After the implementation of model-based OPC, the circuit layout is full of small jig and jag patterns making the failure rate of defect repair higher. In order to reduce cycle time and mask cost, the optimization of both OPC Downloaded From: http://proceedings.spiedigitallibrary.org/ on 06/21/2016 Terms of Use: http://spiedigitallibrary.org/ss/TermsOfUse.aspx algorithm and circuit design needs the closer cooperation between designers, wafer process engineers and mask makers. A close linking of wafer processing, mask making, and OPC as found in captive mask houses is becoming indispensable.

Design of maskless lithography system based on DMD

“…Using maskless lithography has become hot research projects of lithography. In fact, the cost of a mask set could double for each new technology node, resulting in an amazing $3 to $4 million for a state of the art 65-nm mask set in 2005 [1][2][3][4] , This will have a detrimental impact on foundries and application specific integrated circuit (ASIC) fabrications that are finding reticles to be an increasing dominating part of their manufacturing costs, especially for small series production. IMS nanofabrication GmbH developed PLM-2, which can manufacture less than 45 nm.…”

Mask-friendly OPC for a reduced mask cost and writing time

“…Stages like the Model Based Optical Proximity Correction (MBOPC) and Mask Data Preparation (MDP) are gaining more and more into the focus of the microlithography world experts due to their growing impact on both the yield and the Turn Around Time (TAT) of the process and consequently on the Cost of Ownership (CoO) for the technology vendors, whether they are Integrated Device Manufacturers (IDMs), pure running fabs or even Mask shops [1]. Table 1 summarizes the different technology nodes and the increasing complexity with each node.…”

Full size Euclid grism prototype made by photolithography: first optical performance validation

“…In January 2010, we started a R&D program funded by the Centre National d'Etudes Spatiales (CNES) to develop grism manufacturing by the photolithographic process [6,7] which is well adapted to coarse gratings. In addition, another advantage of this method with respect to conventional ones is its ability to write curved and non-equidistant grooves.…”