Masked Dual-Rail Precharge Logic Encounters State-of-the-Art Power Analysis Methods

Moradi, Amir; Kirschbaum, Mario; Eisenbarth, Thomas; Paar, Christof

doi:10.1109/tvlsi.2011.2160375

Cited by 30 publications

(19 citation statements)

References 25 publications

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“…So, this part of the circuit is not repeated in other decoupling circuits. The second decoupling circuit is composed of transistors T 11 -T 18 , and the third one from transistors T 19 -T 26 .…”

Section: Concept Of the Circuitmentioning

confidence: 99%

“…We should here emphasize that both WDDL and MDPL have known security issues (e.g., early propagation [25]), which prevent them to be considered as secure solutions. Further, it has been shown in [26] that sophisticated attacks can also overcome the security provided by iMDPL. One advantage of our proposed scheme is its null frequency overhead, which cannot be achieved by any other countermeasure in the same field.…”

Section: Test Chipmentioning

confidence: 99%

See 1 more Smart Citation

A Hardware-Based Countermeasure to Reduce Side-Channel Leakage: Design, Implementation, and Evaluation

Gornik

Moradi

Oehm

et al. 2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Side-channel attacks are one of the major concerns for security-enabled applications as they make use of information leaked by the physical implementation of the underlying cryptographic algorithm. Hence, reducing the side-channel leakage of the circuits realizing the cryptographic primitives is amongst the main goals of circuit designers. In this paper, we present a novel circuit concept, which decouples the main power supply from an internal power supply that is used to drive a single logic gate. The decoupling is done with the help of buffering capacitances integrated into semiconductor. We also introduce-compared to the previously known schemes-an improved decoupling circuit which reduces the crosstalk from the internal to the external power supply. The result of practical side-channel evaluation on a prototype chip fabricated in a 150 nm CMOS technology shows a high potential of our proposed technique to reduce the side-channel leakages.

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Section: Concept Of the Circuitmentioning

confidence: 99%

Section: Test Chipmentioning

confidence: 99%

A Hardware-Based Countermeasure to Reduce Side-Channel Leakage: Design, Implementation, and Evaluation

Gornik

Moradi

Oehm

et al. 2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…iMDPL improves MDPL by adding an evaluation precharge detection unit that may prevent the occurrence of early propagation [18]. However, the imbalance between the two rails still leaks information [21] We investigate the impact of NBTI aging on power analysis of cryptographic devices. In particular, we analyze the NBTI aging effect on MDPL and gate-level masking against CPA and template attack.…”

Section: Introductionmentioning

confidence: 99%

Simulation and analysis of negative-bias temperature instability aging on power analysis attacks

Guo

Karimi

Regazzoni³

et al. 2015

2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)

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Transistor aging is an important failure mechanism in nanoscale designs and is a growing concern for the reliability of future systems. Transistor aging results in circuit performance degradation over time and the ultimate circuit failure. Among aging mechanisms, Negative-Bias Temperature Instability (NBTI) has become the leading limiting factor of circuit lifetime. While the impact of transistor aging is well understood from the device point of view, very little is known about its impact on security, and in particular on power analysis attack. This paper fills the gap by evaluating the effects on power analysis attack. Our experimental results obtained using PRESENT algorithm show that CPA attacks are not significantly affected by aging, while the successful rate of template attack changes significantly.

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“…Therefore, some place-and-route methods such as [6,33] have been proposed to diminish the load imbalances of complementary signals in an ASIC design process. Although iMDPL [26], which solves the early propagation effect of MDPL, was designed to relax the necessity of balanced routings, still has exploitable leakages due to imbalanced routing of the dual-rail mask signal [20].…”

Section: Introductionmentioning

confidence: 99%

Early Propagation and Imbalanced Routing, How to Diminish in FPGAs

Moradi

Immler

2014

Advanced Information Systems Engineering

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Abstract. This work deals with DPA-resistant logic styles, i.e., celllevel countermeasures against power analysis attacks that are known as a serious threat to cryptographic devices. Early propagation and imbalanced routings are amongst the well-known issues of such countermeasures, that -if not considered during the design process -can cause the underlying cryptographic device to be vulnerable to certain attacks. Although most of the DPA-resistant logic styles target an ASIC design process, there are a few attempts to apply them in an FPGA platform. This is due to the missing freedom in FPGA design tools required to deal with the aforementioned problems. Our contribution in this work is to provide solutions for both early propagation and imbalanced routings considering a modern Xilinx FPGA as the target platform. Foremost, based on the WDDL concept we design a new FPGA-based logic style without early propagation in both precharge and evaluation phases. Additionally, with respect to the limited routing resources within an FPGA we develop a customized router to find the best appropriate dual-rail routes for a given dual-rail circuit. Based on practical experiments on a Virtex-5 FPGA our evaluations verify the efficiency of each of our proposed approaches. They significantly improve the resistance of the design compared to cases not benefiting from our schemes.

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Masked Dual-Rail Precharge Logic Encounters State-of-the-Art Power Analysis Methods

Cited by 30 publications

References 25 publications

A Hardware-Based Countermeasure to Reduce Side-Channel Leakage: Design, Implementation, and Evaluation

A Hardware-Based Countermeasure to Reduce Side-Channel Leakage: Design, Implementation, and Evaluation

Simulation and analysis of negative-bias temperature instability aging on power analysis attacks

Early Propagation and Imbalanced Routing, How to Diminish in FPGAs

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