Masking timing errors on speed-paths in logic circuits

Abstract

There is a growing concern about timing errors resulting from design marginalities and the effects of circuit aging on speed-paths in logic circuits. This paper presents a low overhead solution for masking timing errors on speed-paths in logic circuits. Error masking at the outputs of a logic circuit is achieved by synthesis of a nonintrusive error-masking circuit that has at least 20% timing slack over the original logic circuit. The error-masking circuit can also be used to collect runtime information when the speed-paths are exercised to (i) predict the onset of wearout and (ii) assist in in-system silicon debug. Simulation results for several benchmark circuits and modules from the OpenSPARC T1 processor are presented to illustrate the effectiveness of the proposed solution. 100% masking of timing errors on all speed-paths within 10% of the critical path delay is achieved for all circuits with an average area (power) overhead of 16% (18%).

TIMBER: Time borrowing and error relaying for online timing error resilience

“…For a multi-stage timing error to occur, multiple critical paths connected end-to-end will have to be sensitized on successive clock cycles. The critical path sensitization probability for the top 10% critical paths is of the order of 10 −4 -10 −8 [13]. Hence, the probability of a multi-stage timing error resulting from sensitization of multiple critical paths on successive clock cycles is negligibly small.…”

“…Logical error masking techniques (e.g., [13]) use redundant logic to compute the correct value of the output with a smaller delay when critical paths are exercised. Temporal error masking techniques mask errors by time-borrowing, i.e., delaying the arrival time of the correct data to the next pipeline stage.…”

“…band before the clock edge. Error masking techniques (e.g., [13]) logically mask timing errors by adding extra logic. Although the dynamic variability timing margin is recovered completely and the system state is always correct, error masking incurs a modest combinational area and power overhead.…”

A new methodology for reduced cost of resilience

“…The outputs of the main combinational logic are compared with those of the duplicated logic in each cycle. Choudhury et al [8] synthesize error-masking circuits and use 2-to-1 multiplexers to mask errors at the output of critical paths. Similarly, Yuan et al [22] mask errors by adding redundant approximation logic which has higher speed than the original circuit.…”

Logic synthesis and circuit customization using extensive external don't-cares

“…While "soft" application domains · 3 such as multimedia can tolerate these situations well, other applications may require an output flag indicating that a given input cannot be processed correctly. To this end, techniques for masking timing errors, such as the work by Choudhury and Mohanram [2009], can be used to generate the flag.…”