Massive metrology using fast e-beam technology improves OPC model accuracy by &gt;2x at faster turnaround time

Zhao, Qian; Wang, Lei; Wang, Jazer; Wang, Chang‐An; Shi, Hanqing; Guerrero, James; Mu, Feng; Zhang, Qiang; Liang, Jiao; Guo, Yinlong; Zhang, Chen; Wallow, Tom; Río, David; Wang, Lester; Wang, Alvin; Wang, Jen-Shiang; Gronlund, Keith; Lang, Jun; Koh, Kar Kit; Zhang, Dong Qing; Krishnamurthy, S.; Fei, Ray; Lin, Chia-Wen; Fang, Wei; Wang, Fei

doi:10.1117/12.2299971

Cited by 4 publications

(3 citation statements)

References 2 publications

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“…Although this approach has many advantages, the time and cost of using conventional CD-SEM metrology to measure such a large amount of CD gauges are prohibitive. By contrast, using large FoV e-beam inspection with an improved training algorithm to extract fine contours from wafer hotspots, a hotspot-aware OPC model can predict ADI hotspots with a higher capture rate as compared to conventional OPC model 7 …”

Section: Resultsmentioning

confidence: 99%

“…By contrast, using large FoV e-beam inspection with an improved training algorithm to extract fine contours from wafer hotspots, a hotspot-aware OPC model can predict ADI hotspots with a higher capture rate as compared to conventional OPC model. 7 The large FOV can cover a design that can be repeated multiple times. In fact, the key factor to improve the model quality is a good confidence level of the measurement inputs, which will directly influence the quality of the simulation predictions.…”

Section: Opcmentioning

confidence: 99%

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Unavoidable renaissance of electron metrology in the age of high numerical aperture extreme ultraviolet lithography

Lorusso

2022

J. Micro/Nanopattern. Mats. Metro.

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Things are drastically changing in the field of metrology. The main reason for that is related to the daunting specification requirements for metrology imposed by high numerical aperture extreme ultraviolet lithography (high NA EUVL). We observe a variety of generation e-beam tools proliferating in imec unique ecosystem, from in-line transmission electron microscope (TEM) to voltage contrast (VC) overlay tools, from die to database (D2DB) large area scanning electron microscope (SEM) to high-voltage SEM, from artificial intelligence (AI)based inspection tools to massive data acquisition e-beam system. We are facing a renaissance of e-beam metrology. We are going to describe the challenges as well as the latest evolutionary developments of e-beam metrology in the semiconductor industry.

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Section: Resultsmentioning

confidence: 99%

Section: Opcmentioning

confidence: 99%

Unavoidable renaissance of electron metrology in the age of high numerical aperture extreme ultraviolet lithography

Lorusso

2022

J. Micro/Nanopattern. Mats. Metro.

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“…1 Therefore, choosing proper sample to calibrate or validate ML model is one of the most important procedure to establish valid model without model error as possible. 2 This is critical for manufacturing logic device in foundry business, especially, due to the complex circuit design which may differ from each chip-making vendors. Thus, even though there have been enormous interests to obtain full chip covering model for logic device with possible design rule, it has been suffered from various types of pattern combination in each mask, while the turnaround time (TAT) obtaining metrology data such as CD or contour, is insufficient.…”

Section: Introductionmentioning

confidence: 99%

Unsupervised ML classification driven process model coverage check

Song

Jeong

Park

et al. 2023

DTCO and Computational Patterning II

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Semiconductor manufacturing’s full chip RET/OPC operations rely on the process models calibrated against metrology data collected from custom designed test structures. Physics-based compact models and machine learning models inherently carry the issue of model coverage often synonymous with calibration test pattern coverage. Therefore, process models frequently fail to predict unseen patterns within error tolerance. With the push for advanced technology node, such events can even occur after a node is declared HVM ready. Foundries have been combating the model coverage deficiency through costly model revisions, or expensive repair flows. There has always been the desire to have capability to screen and enhance compact model of potential coverage issue. In this paper, we use the machine learning clustering platform to learn the signatures of the model calibration test patterns and then compare them to the new design patterns in terms of feature vectors’ space correlated to model parameters’ space. The comparison provides not only the locations of the new patterns but also the similarity ranking with respect to the reference pattern, so that those patterns can be included and be further analyzed for better model coverage. These patterns are often suitable candidates to be included into new model calibration set. In this application, full chip capability is also essential besides the accuracy of the learning. The full-chip pattern check needs to be done quickly and efficiently; hence this technology could be adopted for new chip screening, highlighting areas worth paying extra attention to during inspection.

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