Proceedings of the 59th ACM/IEEE Design Automation Conference 2022
DOI: 10.1145/3489517.3530435
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Cited by 28 publications
(5 citation statements)
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References 7 publications
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“…For example, Reis et al [ 62 ] proposed a computing-in-memory-based HE implementation to gain energy savings of between 266.4 times and 532.8 times for homomorphic multiplications (the most expensive HE operation) compared with a CPU-based HE solution. In addition, Lei et al [ 63 ] proposed an energy-efficient accelerator for fully homomorphic encryption that improves the throughput per Watt by 6.3 times compared with that of previous accelerators.…”
Section: Discussionmentioning
confidence: 99%
“…For example, Reis et al [ 62 ] proposed a computing-in-memory-based HE implementation to gain energy savings of between 266.4 times and 532.8 times for homomorphic multiplications (the most expensive HE operation) compared with a CPU-based HE solution. In addition, Lei et al [ 63 ] proposed an energy-efficient accelerator for fully homomorphic encryption that improves the throughput per Watt by 6.3 times compared with that of previous accelerators.…”
Section: Discussionmentioning
confidence: 99%
“…FPT achieves a massive PBS throughput of 1 PBS / 35𝜇s, which requires only modest off-chip memory bandwidth, and is entirely bound by the logic resources on our target Xilinx Alveo U280 FPGA. This represents almost three orders of magnitude speedup over the popular TFHE software library CONCRETE [12] on an Intel Xeon Silver 4208 CPU at 2.1 GHz, a factor 7.1× speedup over a concurrently-developed FPGA architecture [62], and a factor 2.5× speedup over recent 16nm ASIC emulation experiments [33].…”
Section: Introductionmentioning
confidence: 91%
“…One prior implementation proposing a custom hardware format for TFHE's FFTs is MATCHA [33], who propose to use (integer) Dyadic-Value-Quantized Twiddle Factors (DVQTFs). Our fixed-point parameter analysis improves on MATCHA's in two key ways:…”
Section: Related and Future Workmentioning
confidence: 99%
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“…Strix [99] is an ASIC made for evaluating TFHE over streaming data at high throughput. They achieve over 1067x higher throughput compared to CPU implementation (Concrete), 37x higher throughput over the GPU implementation [100], and 7.4x over the state-of-the-art ASIC called Matcha [101], which was the first ASIC designed for TFHE. In Strix, authors identify that blind rotation operation during the PBS step runs sequentially, leading to significant performance degradation.…”
Section: Fpga and Asicsmentioning
confidence: 99%