Material challenges for wafer level packaging

Ma, B.; Zhang, E.; Sun, Hong; Tong, Q.K.; Savoca, A.

doi:10.1109/isapm.2000.869245

Cited by 7 publications

(2 citation statements)

References 9 publications

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“…However, wafer level process presents great challenges to underfill materials. Not only do they have to be compatible with the single reflow process similar to no-flow underfill, but also be subjected to wafer process such as coating and dicing [10].…”

Section: Introductionmentioning

confidence: 99%

Double-layer no-flow underfill materials and process

Zhang

Wong

2003

IEEE Trans. Adv. Packag.

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The no-flow underfill has been invented and practiced in the industry for a few years. However, due to the interfering of silica fillers with solder joint formation, most no-flow underfills are not filled with silica fillers and hence have a high coefficient of thermal expansion (CTE), which is undesirable for high reliability. In a novel invention, a double-layer no-flow underfill is implemented to the flip-chip process and allows fillers to be incorporated into the no-flow underfill. The effects of bottom layer underfill thickness, bottom layer underfill viscosity, and reflow profile on the solder wetting properties are investigated in a design of experiment (DOE) using quartz chips. It is found that the thickness and viscosity of the bottom layer underfill are essential to the wetting of the solder bumps. Chip scale package (CSP) components are assembled using the double-layer no-flow underfill process. Silica fillers of different sizes and weight percentages are incorporated into the upper layer underfill. With a high viscosity bottom layer underfill, up to 40 wt% fillers can be added into the upper layer underfill and do not interfere with solder joint formation. Index Terms-Assembly yield, design of experiment, flip-chip, no-flow underfill, silica fillers.

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Section: Introductionmentioning

confidence: 99%

Double-layer no-flow underfill materials and process

Zhang

Wong

2003

IEEE Trans. Adv. Packag.

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“…Underfill materials that can be preapplied to either the chip [3] or the substrate [4-51 are potential enablers for increasing the throughput of flip-chip assembly.…”

Section: Introductionmentioning

confidence: 99%

Wafer-applied underfill film laminating

Zenner

Carpenter

Chaudhuri

et al.

2002 Proceedings. 8th International Advanced Packaging Materials Symposium (Cat. No.02TH8617)

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Wafer-applied underfill systems for flip-chip bonding have been developed to overcome throughput limitations imposed by capillary underfill systems. The waferapplied underfill system consists of a highly filled film laminated to a bumped IC wafer and a liquid flux adhesive dispensed on the board. The wafer is diced after film lamination and the individual chips carry the underfill through the assembly process. The flux adhesive is dispensed at the bond site just prior to chip placement. These underfill materials undergo most or all of the required cure through a single reflow oven pass. A critical concern for a successful wafer-applied underfill bond is the prevention of discontinuities or voids in the underfill layer. Voids in the underfill can weaken the solder reinforcement otherwise provided by the underfill or permit the formation of betweenbump shorts caused by solder extruding into the void. The wafer-applied underfill film laminating process presents one possible source for discontinuities. Since the film is laminated to a bumped wafer, the complete encasement around each solder bump by the wafer-applied underfill film is a necessity. A lamination process used to transfer the wafer-applied underfill film to the bumped wafer without such discontinuities will be described. This lamination process has been shown to provide uniform lamination over a full wafer with complete encasement of the solder bumps. Wafer-applied underfill and flux material characteristics and reliability results also will be reported.

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A novel approach for incorporating silica filler into no-flow underfill

Zhang

Lu²,

Wong³

2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)

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Material challenges for wafer level packaging

Cited by 7 publications

References 9 publications

Double-layer no-flow underfill materials and process

Double-layer no-flow underfill materials and process

Wafer-applied underfill film laminating

A novel approach for incorporating silica filler into no-flow underfill

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