Math Toolkit for Real-Time Programming

Crenshaw, Jack W.

doi:10.1201/9781482296747

Cited by 33 publications

(17 citation statements)

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“…Additionally, operations inside the kernels that cannot be directly executed on the PEs of the FCC units are transformed into series of supported operations (ALU and multiplications) whenever it is possible. The divisions can be transformed to shifts, while a square root computation can be performed by the FCCs using a method, like the Friden algorithm [23] that has been implemented in the proposed synthesis methodology. MachineSUIF compiler passes have been developed for the automatic application of the described optimizations on a kernel_s CDFG.…”

Section: Synthesis Methodologymentioning

confidence: 99%

Performance and Energy Consumption Improvements in Microprocessor Systems Utilizing a Coprocessor Data-Path

Galanis

Dimitroulakos

Goutis

2007

J Sign Process Syst Sign Image

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The speedups and the energy reductions achieved in a generic single-chip microprocessor system by employing a high-performance data-path are presented. The data-path acts as a coprocessor that accelerates computational intensive kernel sections thereby increasing the overall performance. The authors have previously introduced the data-path which is composed by flexible computational components (FCCs). These components can realize any two-level sequence of primitive operations. The automated coprocessor synthesis method from high-level software description and its integration to a design flow for executing applications on the system is presented. The overall application speedups of eleven real-life applications, relative to the software execution on the microprocessor, are estimated using the design flow. These speedups are close to theoretical bounds and range from 1.78 to 5.84, having an average value of 3.04, while the overhead in circuit area is small. The energy savings range from 41 to 74%, while the reduction in the application energy-delay product has an average value of 80%. A comparison with another high-performance data-path showed that the proposed coprocessor achieves better performance, consumes less energy and has smaller area-time products for the generated data-paths. Additionally, the FCC data-path achieves better performance in accelerating kernels relative to a VLIW DSP core.

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Section: Synthesis Methodologymentioning

confidence: 99%

Performance and Energy Consumption Improvements in Microprocessor Systems Utilizing a Coprocessor Data-Path

Galanis

Dimitroulakos

Goutis

2007

J Sign Process Syst Sign Image

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“…The argument is suitably implemented with some polynomial approximation which may require a large number of arithmetic and logical operations. See for example [5,9]. The magnitude will essentially require a scalar product of the gradient by itself, followed by a square-root.…”

Section: Weightingmentioning

confidence: 99%

Fast triangular binning kernel approximations for weighted gradient histogram creation

Kristensen

Nilsson

2014

2014 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT)

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Abstract-The implementation of weighted gradient histograms are studied. Such histograms are commonly used in computer vision methods, and their creation can make up a significant portion of the computational cost. Further, due to potentially severe aliasing, non-uniform binning kernels are desirable. We show that previously presented fast methods for uniform binning kernels can be extended to non-uniform binning, and that the triangular kernel can be well approximated for common weighting strategies. The approximation is implemented with sums and products of projections of the gradient samples on specially chosen vectors. Consequently, only a few standard arithmetic operations are required, and therefore, the suggested implementation has a significantly lower computational cost when compared with an implementation in which the gradient argument and magnitude are explicitly evaluated. Finally, the frequency components of the different kernels are studied to quantify the fundamental gain achieved by using triangular kernels instead of uniform kernels.

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“…Furthermore, to accommodate the implementation of operations like divisions or square root computations on the FPGA, these operations are transformed into series of primitive operations, as multiplications and ALU-type ones. For example, the divisions are transformed to shifts, while a square root computation can be decomposed to simpler operations using a method, like the Friden algorithm [36]. The temporal partitioning algorithm partitions the DFG into segments under the constraint of the FPGA area.…”

Section: Description Of the Mapping Proceduresmentioning

confidence: 99%

A method for partitioning applications in hybrid reconfigurable architectures

Galanis

Milidonis

Theodoridis

et al. 2005

Des Autom Embed Syst

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In this paper, we propose a methodology for accelerating application segments by partitioning them between reconfigurable hardware blocks of different granularity. Critical parts are speeded-up on the coarse-grain reconfigurable hardware for meeting the timing requirements of application code mapped on the reconfigurable logic. The reconfigurable processing units are embedded in a generic hybrid system architecture which can model a large number of existing heterogeneous reconfigurable platforms. The fine-grain reconfigurable logic is realized by an FPGA unit, while the coarse-grain reconfigurable hardware by our developed high-performance data-path. The methodology mainly consists of three stages; the analysis, the mapping of the application parts onto fine and coarse-grain reconfigurable hardware, and the partitioning engine. A prototype software framework realizes the partitioning flow. In this work, the methodology is validated using five real-life applications. Analytical partitioning experiments show that the speedup relative to the all-FPGA mapping solution ranges from 1.5 to 4.0, while the specified timing constraints are satisfied for all the applications.

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Math Toolkit for Real-Time Programming

Cited by 33 publications

References 0 publications

Performance and Energy Consumption Improvements in Microprocessor Systems Utilizing a Coprocessor Data-Path

Performance and Energy Consumption Improvements in Microprocessor Systems Utilizing a Coprocessor Data-Path

Fast triangular binning kernel approximations for weighted gradient histogram creation

A method for partitioning applications in hybrid reconfigurable architectures

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