“…The challenge while implementing the systems in FPGAs is to design the fractional order integrator which is not a readily available block in the System Generator [21,22]. Hence we implement the fractional integrators using the mathematical relation [32,33] discussed in (4), (5), and (6) and the value of ℎ is taken as 0.001 with the initial conditions as described in Table 1 and the commensurate fractional order taken as = 0.991 for FONCS-1, = 0.995 for FONCS-2, = 0.989 for FONCS-3, and = 0.99 for FONCS-4. Figures 17, 18(a), and 18(b) show the Xilinx RTL schematics of the FONCS-1 system implemented in Kintex-7 (device = 7k160t, package = fbg484 S), power utilized by the system, and power utilized for various fractional orders, respectively.…”