Maximizing Heterogeneous Processor Performance Under Power Constraints

Abstract

Heterogeneous processors (e.g., ARM's big.LITTLE) improve performance in power-constrained environments by executing applications on the 'little' low-power core and move them to the 'big' high-performance core when there is available power budget. The total time spent on the big core depends on the rate at which the application dissipates the available power budget. When applications with different big-core power consumption characteristics concurrently execute on a heterogeneous processor, it is best to give a larger share of the power budget to applications that can run longer on the big core, and a smaller share to applications that run for a very short duration on the big core.This article investigates mechanisms to manage the available power budget on power-constrained heterogeneous processors. We show that existing proposals that schedule applications onto a big core based on various performance metrics are not high performing, as these strategies do not optimize over an entire power period and are unaware of the applications' power/performance characteristics. We use linear programming to design the DPDP power management technique, which guarantees optimal performance on heterogeneous processors. We mathematically derive a metric (Delta Performance by Delta Power) that takes into account the power/performance characteristics of each running application and allows our power-management technique to decide how best to distribute the available power budget among the co-running applications at minimal overhead. Our evaluations with a 4-core heterogeneous processor consisting of big.LITTLE pairs show that DPDP improves performance by 16% on average and up to 40% compared to a strategy that globally and greedily optimizes the power budget. We also show that DPDP outperforms existing heterogeneous scheduling policies that use performance metrics to decide how best to schedule applications on the big core.

Adaptive Power Shifting for Power-Constrained Heterogeneous Systems

“…Winter et al [8] present different scheduling and power management algorithms on a 256-core architecture. Adileh et al [32], [33] schedule applications into out-of-order or in-order cores based on their performance and power consumption. Some works propose to coordinate the frequencies of the CPU and the memory to maximize performance [26], [34], [35], coordinate DVFS with other techniques such as power gating [11], core allocation [9], [10], and SMT levels [12], save energy [27] under a power cap, and manage power through a resource controller based on market solutions [6] and machine learning models [7].…”

CuttleSys: Data-Driven Resource Management forInteractive Applications on Reconfigurable Multicores

“…Teodorescu [96] proposes LinOpt, a linear programmingbased approach, while [100] explores the Hungarian algorithm to optimize performance under a power budget. Adileh et al [8,9] maximizes performance by multiplexing applications between two voltage/frequency operating points to match the power budget. The authors propose a technique to shift "power holes" arising due to core heterogeneity.…”