Maximizing yield in Near-Threshold Computing under the presence of process variation

Abstract

Abstract-Near-Threshold Computing (NTC) shows potential to provide significant energy efficiency improvements as it alleviates the impact of leakage in modern deep sub-micron CMOS technology. As the gap between supply and threshold voltage shrink, however, the energy efficiency gains come at the cost of device performance variability. Thus, adopting nearthreshold in modern CAD flows requires careful consideration when addressing commonly targeted objectives. We propose a process variation-aware near-threshold voltage (P V -Nvt) gate sizing framework for minimizing power subject to performance yield constraints. We evaluate our approach using an industrialflow on a set of modern benchmarks. Our results show our method achieves significant improvement in leakage power, while meeting performance yield targets, over a state-of-the-art method that does not consider near-threshold computing.

A temperature-aware synthesis approach for simultaneous delay and leakage optimization

“…Temperature-aware dual V t and gate sizing was explored [15] and uses heuristics to place high V t in hot regions; however, they consider simplified leakage and delay models for accounting for power and timing values. Gate sizing has been explored in Near-threshold computing [4] [25].…”