Maximum benefit from a minimal HTM

Hofmann, Owen S.; Rossbach, Christopher J.; Witchel, Emmett

doi:10.1145/1508284.1508262

Cited by 4 publications

(5 citation statements)

References 33 publications

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“…One way of limiting the complexity required by an HTM is to provide a limited best-effort HTM that falls back to an STM if it is unable to proceed [12,14,20,22,38]. These systems are particularly well-suited for supporting lock-elision and small transactions.…”

Section: Hybridtmmentioning

confidence: 99%

Hardware acceleration of transactional memory on commodity systems

et al. 2011

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The adoption of transactional memory is hindered by the high overhead of software transactional memory and the intrusive design changes required by previously proposed TM hardware. We propose that hardware to accelerate software transactional memory (STM) can reside outside an unmodified commodity processor core, thereby substantially reducing implementation costs. This paper introduces Transactional Memory Acceleration using Commodity Cores (TMACC), a hardware-accelerated TM system that does not modify the processor, caches, or coherence protocol.We present a complete hardware implementation of TMACC using a rapid prototyping platform. Using this hardware, we implement two unique conflict detection schemes which are accelerated using Bloom filters on an FPGA. These schemes employ novel techniques for tolerating the latency of fine-grained asynchronous communication with an out-of-core accelerator. We then conduct experiments to explore the feasibility of accelerating TM without modifying existing system hardware. We show that, for all but short transactions, it is not necessary to modify the processor to obtain substantial improvement in TM performance. In these cases, TMACC outperforms an STM by an average of 69% in applications using moderate-length transactions, showing maximum speedup within 8% of an upper bound on TM acceleration. Overall, we demonstrate that hardware can substantially accelerate the performance of an STM on unmodified commodity processors.

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Section: Hybridtmmentioning

confidence: 99%

Hardware acceleration of transactional memory on commodity systems

et al. 2011

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“…This ad hoc solution will not apply to general-purpose programming, especially in the presence of composing transactions with standard library routines. Calling standard libraries and system calls, such as futex, within a transaction will likely require a combination of new standard libraries [35], OS support [28], or a TM implementation-specific solution like making a single transaction non-speculative [3,8,12].…”

Section: Memory Allocationmentioning

confidence: 99%

Understanding transactional memory performance

Porter

Witchel

2010

2010 IEEE International Symposium on Performance Analysis of Systems &Amp; Software (ISPASS)

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Abstract-Transactional memory promises to generalize transactional programming to mainstream languages and data structures. The purported benefit of transactions is that they are easier to program correctly than fine-grained locking and perform just as well. This performance claim is not always borne out because an application may violate a common-case assumption of the TM designer or because of external system effects. This paper carefully studies a range of factors that can adversely influence transactional memory performance.In order to help programmers assess the suitability of their code for transactional memory, this paper introduces a formal model of transactional memory as well as a tool, called Syncchar. Syncchar can predict the speedup of a conversion from locks to transactions within 25% for the STAMP benchmarks. We also use the Syncchar tool to diagnose and eliminate a starvation pathology in the TxLinux kernel, improving the performance of the Modified Andrew Benchmark by 55% over Linux.The paper also presents the first detailed study of how the performance of user-level transactional programs (from the STAMP benchmarks) are influenced by factors outside of the transactional memory system. The study includes data about the interaction of transactional programs with the architecture, memory allocator, and compiler. Because many factors influence the performance of transactional programs, getting good performance from transactions is more difficult than commonly appreciated.

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“…MetaTM/TxLinux [80,81,50] is one of the first efforts to evaluate the impact of large-scale operating system code on the performance of hardware transactional memory systems. MetaTM is the hardware transactional memory implementation that supports TxLinux, a Linux version that is modified to use transactions.…”

Section: Metatm/txlinuxmentioning

confidence: 99%

“…Further, a new policy called SizeMatters is also implemented, which favours transactions with large working sets. In [50] is shown how MetaTM can be combined with a software transactional memory system to form a hybrid transactional memory system.…”

Section: Metatm/txlinuxmentioning

confidence: 99%

Transactional memory

Grahn¹

2010

Journal of Parallel and Distributed Computing

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Current and future processor generations are based on multicore architectures where the performance increase comes from an increasing number of cores on a chip. In order to utilize the performance potential of multicore architectures the programs also need to be parallel, but writing parallel programs is a non-trivial task. Transactional memory tries to ease parallel program development by providing atomic and isolated execution of code sequences, enabling software composability and protected access to shared data. In addition, transactional memory has the ability to execute atomic code sequences in parallel as long as no data conflicts occur. Transactional memory implementation proposals exist for both hardware and software, as well as hybrid solutions. This special issue on transactional memory introduces transactional memory as a concept, presents an overview of some of the most important approaches so far, and finally, includes five articles that advances the state-of-the-art in transactional memory research.

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Maximum benefit from a minimal HTM

Cited by 4 publications

References 33 publications

Hardware acceleration of transactional memory on commodity systems

Hardware acceleration of transactional memory on commodity systems

Understanding transactional memory performance

Transactional memory

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