MaxSim: A simulation platform for managed applications

Rodchenko, Andrey; Kotselidis, Christos; Nisbet, Andy; Pop, Antoniu; Luján, Mikel

doi:10.1109/ispass.2017.7975286

Cited by 11 publications

(10 citation statements)

References 44 publications

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“…Two platforms today enable executing Java applications on top of simulated hardware in a reasonable amount of time: (1) Jikes RVM on top of Sniper [44], and (2) Maxine VM on top of ZSim [42]. Both Sniper and ZSim are cycle-level multicore simulators that trade off accuracy for speed [15], [43].…”

Section: A Evaluation Methodologiesmentioning

confidence: 99%

Emulating and Evaluating Hybrid Memory for Managed Languages on NUMA Hardware

Akram

Sartor

McKinley

et al. 2019

2019 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)

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Non-volatile memory (NVM) has the potential to become a mainstream memory technology and challenge DRAM. Researchers evaluating the speed, endurance, and abstractions of hybrid memories with DRAM and NVM typically use simulation, making it easy to evaluate the impact of different hardware technologies and parameters. Simulation is, however, extremely slow, limiting the applications and datasets in the evaluation. Simulation also precludes critical workloads, especially those written in managed languages such as Java and C#. Good methodology embraces a variety of techniques for evaluating new ideas, expanding the experimental scope, and uncovering new insights. This paper introduces a platform to emulate hybrid memory for managed languages using commodity NUMA servers. Emulation complements simulation but offers richer software experimentation. We use a thread-local socket to emulate DRAM and a remote socket to emulate NVM. We use standard C library routines to allocate heap memory on the DRAM and NVM sockets for use with explicit memory management or garbage collection. We evaluate the emulator using various configurations of write-rationing garbage collectors that improve NVM lifetimes by limiting writes to NVM, using 15 applications and various datasets and workload configurations. We show emulation and simulation confirm each other's trends in terms of writes to NVM for different software configurations, increasing our confidence in predicting future system effects. Emulation brings novel insights, such as the non-linear effects of multi-programmed workloads on NVM writes, and that Java applications write significantly more than their C++ equivalents. We make our software infrastructure publicly available to advance the evaluation of novel memory management schemes on hybrid memories.

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Section: A Evaluation Methodologiesmentioning

confidence: 99%

Emulating and Evaluating Hybrid Memory for Managed Languages on NUMA Hardware

Akram

Sartor

McKinley

et al. 2019

2019 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)

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“…We evaluate Zippads using MaxSim [38], a simulation platform that combines ZSim [39], a Pin-based [27] simulator, and Maxine [54], a 64-bit metacircular research JVM.…”

Section: Methodsmentioning

confidence: 99%

Compress Objects, Not Cache Lines

Tsai

Sánchez

2019

Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Syst

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Existing cache and main memory compression techniques compress data in small fixed-size blocks, typically cache lines. Moreover, they use simple compression algorithms that focus on exploiting redundancy within a block. These techniques work well for scientific programs that are dominated by arrays. However, they are ineffective on object-based programs because objects do not fall neatly into fixed-size blocks and have a more irregular layout. We present the first compressed memory hierarchy designed for object-based applications. We observe that (i) objects, not cache lines, are the natural unit of compression for these programs, as they traverse and operate on object pointers; and (ii) though redundancy within each object is limited, redundancy across objects of the same type is plentiful. We exploit these insights through Zippads, an object-based compressed memory hierarchy, and COCO, a cross-object-compression algorithm. Building on a recent object-based memory hierarchy, Zippads transparently compresses variable-sized objects and stores them compactly. As a result, Zippads consistently outperforms a state-of-theart compressed memory hierarchy: on a mix of array-and object-dominated workloads, Zippads achieves 1.63× higher compression ratio and improves performance by 17%. CCS Concepts • Computer systems organization → Processors and memory architectures.

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“…Without loss of generality, we select the Sniper simulator [11], [13] to showcase our validation methodology. We observe that although x86 and ARM ISA are widely recognized as the two most popular ISAs, most modern simulators support only the x86 ISA, see for example gem5 [2], MARSS [6], Multi2Sim [7], Sniper [13], ZSim [12], PTLSim [4] and MaxSim [28]. Apart from several functional simulators [8], [10], including ARM Fast Models 2 , gem5 is the only widelyused cycle-level timing simulator that supports the ARM AArch64 ISA.…”

Section: B Snipermentioning

confidence: 99%

Racing to Hardware-Validated Simulation

Adileh

Gonzalez-Alvarez

Haro

et al. 2019

2019 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)

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Processor simulators rely on detailed timing models of the processor pipeline to evaluate performance. The diversity in real-world processor designs mandates building flexible simulators that expose parts of the underlying model to the user in the form of configurable parameters. Consequently, the accuracy of modeling a real processor relies on both the accuracy of the pipeline model itself, and the accuracy of adjusting the configuration parameters according to the modeled processor. Unfortunately, processor vendors publicly disclose only a subset of their design decisions, raising the probability of introducing specification inaccuracies when modeling these processors. Inaccurately tuning model parameters deviates the simulated processor from the actual one. In the worst case, using improper parameters may lead to imbalanced pipeline models compromising the simulation output. Therefore, simulation models should be hardware-validated before using them for performance evaluation. As processors increase in complexity and diversity, validating a simulator model against real hardware becomes increasingly more challenging and time-consuming. In this work, we propose a methodology for validating simulation models against real hardware. We create a framework that relies on micro-benchmarks to collect performance statistics on real hardware, and machine learning-based algorithms to fine-tune the unknown parameters based on the accumulated statistics. We overhaul the Sniper simulator to support the ARM AArch64 instruction-set architecture (ISA), and introduce two new timing models for ARM-based in-order and out-oforder cores. Using our proposed simulator validation framework, we tune the in-order and out-of-order models to match the performance of a real-world implementation of the Cortex-A53 and Cortex-A72 cores with an average error of 7% and 15%, respectively, across a set of SPEC CPU2017 benchmarks.

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MaxSim: A simulation platform for managed applications

Cited by 11 publications

References 44 publications

Emulating and Evaluating Hybrid Memory for Managed Languages on NUMA Hardware

Emulating and Evaluating Hybrid Memory for Managed Languages on NUMA Hardware

Compress Objects, Not Cache Lines

Racing to Hardware-Validated Simulation

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