Maze Routing Steiner Trees With Delay Versus Wire Length Tradeoff

Hentschke, Renato Fernandes; Narasimhan, Jagannathan; Johann, Marcelo; Reis, Ricardo

doi:10.1109/tvlsi.2009.2019798

Cited by 13 publications

(4 citation statements)

References 27 publications

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“…The Global Routing step defines routing spaces that will be used for interconnections. The Detailed Routing is responsible for the definition of the exact location of each connection, including the definition of layers and contacts/vias, in the assigning routes defined by the Global Routing [16] [17] [18] [19].…”

Section: ) Routing Toolsmentioning

confidence: 99%

EDA: Overview and Some Trends

Reis¹

2022

JICS

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The development of any integrated circuit depends heavily on the quality of the EDA (Electronic Design Automation) tools used in the design flow. Improved CAD tools and algo-rithms are needed to cope with new fabrication technology requirements, advanced performance constraints, or simply the enormous number of elements involved. In this paper it is giving an overview of the importance of automation in the design process, and it is done a survey of different types of tools presenting some classifications of the tools. Then some few trends on EDA that are needed to deal with the evolution of manufacturing processes will be presented. Some optimi-zation techniques will be presented for selected physical de-sign problems (layout). An important aspect of the design is to reduce power consumption at all levels of abstraction. Power optimization is fundamental in nanoCMOS and in the IoT world. At logic and physical levels, one approach that can be used to optimize the circuit, especially reducing static leakage power and using the automatic generation of the cell layout. With on-the-fly cell generation, the same function can be implemented with a reduced number of transistors, requiring less area and significantly optimizing power and performance. Finally, the use of estimation and visualiza-tion tools is equally important. They can be applied either in the design flow or in the tool's development and research en-vironments as a way to observe and understand the behavior and interactions of algorithms and their operation on real designs and benchmarks.

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Section: ) Routing Toolsmentioning

confidence: 99%

EDA: Overview and Some Trends

Reis¹

2022

JICS

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“…The resultant path is guaranteed to be optimal if the heuristic estimator is admissible. A* heuristics have been widely applied in general purpose routing algorithms [7] [8].…”

Section: A Shortest Path Generation For the Initial Routingmentioning

confidence: 99%

Improved delay-matching bus routing by using multi-layers

Yang

Watanabe

2015

2015 International Conference on Electronic Packaging and iMAPS All Asia Conference (ICEP-IAAC)

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Recently, signal propagation delay in VLSI or PCB becomes a very critical problem due to the increasing clock frequency, where signal delay should be adjusted to meet the requirement of the delay time. The delay can be roughly estimated by the net length. While, due to the circuit complexity and the high density of integration, a single layer routing may not be enough for delay estimation. In recent research, there's a highly efficient algorithm for length matching bus routing for signal delay. However, it doesn't put the high density of integration into consideration. The purpose of this paper is to route several nets by using multiple layers on a high density board to meet the signal delay requirement, even if there exist obstacles in the routing area. Previous research put focus on the single layer routing without considering the complexity and density of the board. In this paper, the complexity and density are taken into account. In our proposed algorithm, the routing area is divided into subareas to solve the problem efficiently, some searching vertices will be set in advance and nets can be assigned to the proper layers to avoid obstacles. After the net assignment, path generation is executed. Then, some optimizations are made to meet the signal delay for each net. Finally, the routing paths of nets which satisfy the delay constraint are determined. Experimental results show that our proposed method is highly effective and efficient.

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“…13 Best delay choice between a set of tradeoff solutions between SMTs and SPTs 14 Trees where the optimization of the critical sink is privileged. 15 The tree construction is guided by an EDM routine call. The same is valid for the SERT-C algorithm, however, the optimization of the critical sink have a higher priority on it.…”

Section: B Routing Algorithmsmentioning

confidence: 99%

“…In a research work, delay can be measured by reduced order models or electrical simulation, however, EDM has been used since the nineties [10] until nowadays [11][12] [13][14] [15], when new algorithms are reported and compared to the previous ones. Then the question is: why is it used if there are more accurate alternatives for measuring delays?…”

Section: Introductionmentioning

confidence: 99%

The Fidelity Property of the Elmore Delay Model in actual comparison of routing algorithms

Santos

Reimann

Johann

et al. 2010

2010 IEEE International Conference on Computer Design

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Despite the existence of several other alternatives for estimating delay of interconnects, the Elmore Delay Model still has been used for comparison of routing algorithms. The criterion used to establish Elmore's model as a confident metric for this purpose is the so-called Fidelity Property. In this work we investigate the Fidelity Property using nowadays interconnect parameters, in four routing scopes. For the first time the Fidelity is evaluated in actual algorithms comparison, one of the main utilities it was established for. What is found is that the original methodology used to evaluate this property hides a significant standard deviation. This standard deviation strongly impacts the capacity of Elmore's model to provide good certainty of choosing the best routing solutions among several ones. Additionally, the experiments of algorithms comparison show that different routing alternatives are appropriated for different routing scopes, with respect to metal layers, driver strengths and routing areas.978-1-4244-8935-0/10/$26.00 ©2010 IEEE

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Maze Routing Steiner Trees With Delay Versus Wire Length Tradeoff

Cited by 13 publications

References 27 publications

EDA: Overview and Some Trends

EDA: Overview and Some Trends

Improved delay-matching bus routing by using multi-layers

The Fidelity Property of the Elmore Delay Model in actual comparison of routing algorithms

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