MBBench: WCET Kıyaslama Kümesi

Kuzhan, Metin; Şahin, Veysel Harun

doi:10.35377/saucis.03.01.705777

Cited by 3 publications

(1 citation statement)

References 16 publications

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“…It is also open source and includes several sequential and parallel benchmark programs written in C programming language. MBBench [24] is another open source WCET benchmark suite. Its main focus is measurement-based WCET analysis tools.…”

Section: Related Workmentioning

confidence: 99%

ABench2020: A WCET Benchmark Suite in Ada Programming Language

Gökçe¹,

Şahin²

2020

acperpro

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Validation is an important part of the development process of real-time systems. During validation, it should be proved that, the system meets its timing constraints. Therefore, worst-case execution time (WCET) analysis is performed. Currently, several WCET analysis tools are being developed. Researchers who develop new WCET analysis tools, need benchmarks to evaluate and compare their tools with alternatives. These benchmarks are called WCET benchmarks. In this paper a new WCET benchmark suite named ABench2020 is introduced. Its main focus is to provide benchmark programs in Ada programming language for WCET research. Therefore, ABench2020 includes several benchmark programs which were written in Ada programming language. The benchmark programs implement different program structures and properties to help researchers test their systems from different aspects. ABench2020 was published as open source. It is freely available over the Internet.

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Section: Related Workmentioning

confidence: 99%

ABench2020: A WCET Benchmark Suite in Ada Programming Language

Gökçe¹,

Şahin²

2020

acperpro

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BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration Framework

Chen

Sun

Zhai

et al. 2021

2021 IEEE/ACM International Conference on Computer Aided Design (ICCAD)

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BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration

Bai,

Sun,

Zhai

et al. 2023

ACM Trans. Des. Autom. Electron. Syst.

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Microarchitecture parameters tuning is critical in the microprocessor design cycle. It is a non-trivial design space exploration (DSE) problem due to the large solution space, cycle-accurate simulators’ modeling inaccuracy, and high simulation runtime for performance evaluations. Previous methods require massive expert efforts to construct interpretable equations or high computing resource demands to train black-box prediction models. This paper follows the black-box methods due to better solution qualities than analytical methods in general. We summarize two learned lessons and propose BOOM-Explorer accordingly. First, embedding microarchitecture domain knowledge in the DSE improves the solution quality. Second, BOOM-Explorer makes the microarchitecture DSE for register-transfer-level designs within the limited time budget feasible. We enhance BOOM-Explorer with the diversity-guidance, further improving the algorithm performance. Experimental results with RISC-V Berkeley-Out-of-Order Machine under 7-nm technology show that our proposed methodology achieves an average of \(18.75\% \) higher Pareto hypervolume, \(35.47\% \) less average distance to reference set, and \(65.38\% \) less overall running time compared to previous approaches.

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MBBench: WCET Kıyaslama Kümesi

Cited by 3 publications

References 16 publications

ABench2020: A WCET Benchmark Suite in Ada Programming Language

ABench2020: A WCET Benchmark Suite in Ada Programming Language

BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration Framework

BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration

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