MCMM clock tree optimization based on slack redistribution using a reduced slack graph

Ewetz, Rickard; Koh, Cheng-Kok

doi:10.1109/aspdac.2016.7428039

Cited by 6 publications

(5 citation statements)

References 15 publications

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“…Finally, to satisfy both skew constraints and latency bound, a concept of a feasible skew-latency range (FSLR) is introduced, which is the intersection of an FSR in Eq (9) and an FLR in Eq (12) as follows:…”

Section: Derivation Of Fdirs and Flrsmentioning

confidence: 99%

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Construction of Latency-Bounded Clock Trees

Ewetz

Tan

Koh

2016

Proceedings of the 2016 on International Symposium on Physical Design

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Clock trees must be constructed to function even under the influence of on-chip variations (OCV). Bounding the latency of a clock tree, i.e., the maximum delay from the tree root to any sequential element, is important because the latency correlates with the maximum magnitude of the skews caused by OCV. In this paper, a latency constraint graph (LCG) that captures the latencies of a set of subtrees and the skew constraints between the subtrees is introduced. The minimum latency of a clock tree that can be constructed from the corresponding subtrees is equal to the (negative of the) length of a shortest path in the LCG, which can be computed in O(V E). Based on the LCG, we propose a framework that consists of a latency-aware clock tree synthesis (CTS) phase and a clock tree optimization (CTO) phase to construct latency-bounded clock trees. When applied to a set of synthesized circuits, the framework is capable of constructing latency-bounded clock trees that have higher yield compared to clock trees constructed in previous studies.

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Section: Derivation Of Fdirs and Flrsmentioning

confidence: 99%

“…The CTO phase is based on the techniques proposed in [9]. The optimization aims to remove timing violations (or negative slacks, i.e., TNS and WNS) in a clock tree by realizing non-negative delay adjustments.…”

Section: Clock Tree Optimization (Cto) Phasementioning

confidence: 99%

Construction of Latency-Bounded Clock Trees

Ewetz

Tan

Koh

2016

Proceedings of the 2016 on International Symposium on Physical Design

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“…The optimization is performed by realizing delay adjustments in the tree by inserting buffers and detour wires. The delay adjustments are specified using an LP formulation [14,15,9]. For further technical details of the CTO phase, please refer to [14,15,9].…”

Section: Evaluation Of Robustness To Ocvmentioning

confidence: 99%

“…The delay adjustments are specified using an LP formulation [14,15,9]. For further technical details of the CTO phase, please refer to [14,15,9]. To facilitate a fair comparison with [8,10], we apply CTO [14,15,9] to the RTS-UST structures constructed by our framework.…”

Section: Evaluation Of Robustness To Ocvmentioning

confidence: 99%

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Clock Tree Construction based on Arrival Time Constraints

Ewetz

Koh

2017

Proceedings of the 2017 ACM on International Symposium on Physical Design

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There are striking differences between constructing clock trees based on dynamic implied skew constraints and based on static arrival time constraints. Dynamic implied skew constraints allow the full timing margins to be utilized, but the constraints are required to be updated (with high time complexity). In contrast, static arrival time constraints are decoupled and are not required to be updated. Therefore, the constraints can be obtained in constant time, which facilitates the exploration of various tree topologies. On the other hand, arrival time constraints do not allow the full timing margins to be utilized. Consequently, there is a tradeoff between topology exploration and timing margin utilization. In this paper, the advantages of static arrival time constraints are leveraged to construct clock trees with useful skew while exploring various tree topologies. Moreover, the constraints are specified and respecified throughout the synthesis process reduce the cost of the constructed clock trees. It is experimentally demonstrated that the proposed approach results in clock trees with 16% lower average capacitive cost compared with clock trees constructed based on dynamic implied skew constraints.

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