Measurement and Analysis of Parasitic Capacitance in FinFETs with High-k Dielectrics and Metal-Gate Stack

Dixit, Abhisek; Bandhyopadhyay, Anirban; Collaert, N.; Meyer, K. De; Jurczak, M.

doi:10.1109/vlsi.design.2009.80

Cited by 2 publications

(4 citation statements)

References 14 publications

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“…Estimating parasitic capacitance has many uses, like providing a way to compare the efficiency of different layouts. It is also helpful for accurately estimating gate capacitance and, to some extent, reflects the effective channel length of the transistors [3,4]. Since finFET is an alternative and silicon-on-insulator architecture differs from planar MOSFET in terms of layout and layer stacking, many of these capacitors likely have different values in finFET.…”

Section: Finfet Transistormentioning

confidence: 99%

“…They may cause the machine to drift or lead to other erratic behaviors if associated with sensors. Electro-mechanical model of the microelectromechanical system with parasitic capacitance [3,4] To minimize the effect of parasitic capacitance, MEMS designers often consider optimizing the device's physical structure and material characteristics. They may also take other steps to isolate parasitic capacitors, such as shielding or narrowing electrode spacing.…”

Section: Mems Devicementioning

confidence: 99%

“…Figure2. Electro-mechanical model of the microelectromechanical system with parasitic capacitance[3,4] …”

mentioning

confidence: 99%

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The parasitic capacitance considerations of metal interconnects in sub 10 nm era

2024

J. Phys.: Conf. Ser.

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With the development of the integrated circuit industry and semiconductor technology, we have entered the sub-10 nanometers era, which means the distance between adjacent components in a device is less than 10 nm. This is a situation where the parasitic capacitance of metal interconnects must be considered. Parasitic capacitance can act as a significant influence in different ways on disparate devices. Fin field-effect transistors and microelectromechanical systems are typical devices and deserve further detailed explanation on their parasitic capacitance. There are many ways to reduce parasitic capacitance and its attendant effects, including using materials with low dielectric constants and optimizing the structure of the layout. Some others are newly brought out in recent years due to advanced industrial technology and new materials, including carbon nanotubes, oxide-free spacer layers, and tunneling hybrid technology. All these methods are of great significance and practicability to producing and applying semiconductor devices and structures. Knowing more about this expertise about parasitic capacitance can help us better understand its nature and specialties.

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Section: Finfet Transistormentioning

confidence: 99%

Section: Mems Devicementioning

confidence: 99%

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The parasitic capacitance considerations of metal interconnects in sub 10 nm era

2024

J. Phys.: Conf. Ser.

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“…FinFET performance is negatively impacted when the parasitic capacitance between the source/drain contact and metal gate is high. The inclusion of a metal gate recess at the gate can help reduce capacitance but increases metal gate resistance [1][2][3][4][5][6]. Different metal gate recess profiles can be used to help balance the tradeoff between resistance and capacitance.…”

Section: Introductionmentioning

confidence: 99%

The effect of metal gate recess profile on FinFET performance

Nanja,

Lowe,

Sarkar

2024

DTCO and Computational Patterning III

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In FinFET transistors, the parasitic capacitance between the source/drain contact and the metal gate tends to be high, and this can negatively impact device performance. Adding a metal gate recess step can reduce capacitance, but unfortunately it also increases the metal gate resistance. By changing the metal gate recess profile, a good balance between resistance and capacitance can be achieved to reduce RC. In this work, we investigate FinFET metal gate recess profile settings and how changes in profile settings affect FinFET resistance and parasitic capacitance (R and C). Metal gate recess dimensional changes and profile changes can modify parasitic capacitance and impact electrical performance. We performed a virtual DOE where we varied the gate CD, recess depths, and metal gate recess profiles to understand the impact of these changes on FinFET resistance, capacitance, and electrical performance. Different recess profiles, such as sharp head and antenna shapes, were simulated using SEMulator3D® virtual process fabrication and pattern dependence modeling. Subsequent electrical analysis was performed to extract resistance and capacitance values and to model device transistor behavior. We replicated the process to calculate the resistance and capacitance for a GAAFET, and investigated performance trends during changes in gate CD, tungsten (W) etchback and recess profile variations.

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Measurement and Analysis of Parasitic Capacitance in FinFETs with High-k Dielectrics and Metal-Gate Stack

Cited by 2 publications

References 14 publications

The parasitic capacitance considerations of metal interconnects in sub 10 nm era

The parasitic capacitance considerations of metal interconnects in sub 10 nm era

The effect of metal gate recess profile on FinFET performance

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