Measurement And Tridimensional Simulation Of Silicon Pixel Detector Capacitance

Bosisio, L.; Forti, F.; Tomacruz, E.

doi:10.1109/nssmic.1993.701688

Cited by 4 publications

(1 citation statement)

References 7 publications

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“…A standard latch-up problem, which requires over 50,000 irregular grid nodes, may take five hours to simulate on vector machines such as the Cray-2 [6]. Other applications such as SOl, parasitic MOSFETs [7], and silicon pixel detectors [8] may require more computational power. Although faster vector supercomputers may offer the computational power needed, parallel processors provide an attractive alternative.…”

Section: : Introductionmentioning

confidence: 99%

A parallel iterative linear solver for solving irregular grid semiconductor device matrices

Tomacruz¹,

Sanghavi²,

Sangiovanni-Vincentelli³

1994

Proceedings of the 1994 ACM/IEEE Conference on Supercomputing - Supercomputing '94

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We present the use of parallel processors for the solution of drift-diffusion semiconductor device equations using an irregular grid discretization. Preconditioning, partitioning, and communication scheduling algorithms are developed to implement an efficient and robust iterative linear solver with preconditioning. The parallel program is executed on a 64 node CM-5 and is compared with PILS running on a single processor. We observe an efficiency increase in obtaining parallel speed-ups as the problem size increases. We obtain 60% efficiency for CGS with no preconditioning for large problems. Using CGS with processor ILU and magnitude threshold fill-in preconditioning for the CM-5 and CGS with ILU for PILS, we attain 50% efficiency for the solution of the large matrices. 1: IntroductionThe simulation of complex three-dimensional semiconductor devices requires computers with significant computational power. [1,2,3,4] have shown how massively parallel computers can be used efficiently for drift-diffusion device simulation. All these simulators used rectangular grids since they are easy to implement, have perfect load balance, and have regular communication patterns. However, irregular grids are important in the field of device simulations since they allow the modeling of nonrectangular device boundaries and do not require grids for quasi-neutral regions. [5] gives an example of a diagonal alpha particle track that would require 2,000,000 rectangular grid points to model accurately whereas a general irregular grid would only require 6900 grid points to achieve the same accuracy. Even with the reduction of grid points obtained by the use of irregular grids, semiconductor simulation still requires significant computational power. A standard latch-up problem, which requires over 50,000 irregular grid nodes, may take five hours to simulate on vector machines such as the Cray-2 [6]. Other applications such as SOl, parasitic MOSFETs [7], and silicon pixel detectors [8] may require more computational power. Although faster vector supercomputers may offer the computational power needed, parallel processors provide an attractive alternative.We present a Connection Machine 5 (CM-5) [9] device simulator that uses an irregular grid automatically generated by the Omega program [10,11]. For sequential device simulators, the nonlinear algebraic system of equations arising from the discretization is efficiently and accurately solved by a variation of the basic Newton-Raphson algorithm. As usual in this algorithm, most of the computation time is spent on the solution of the linearized system of equations. The focus of our work is to speed-up this step. We present heuristics for partitioning, communication scheduling, and preconditioning for the efficient implementation of a parallel iterative linear solver. Parallel results are compared with a sequential program called PILS [12].This paper is organized as follows. An overview of the device equations and how they are generally solved is first given. Section 3 describes a parallel line...

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Section: : Introductionmentioning

confidence: 99%

A parallel iterative linear solver for solving irregular grid semiconductor device matrices

Tomacruz¹,

Sanghavi²,

Sangiovanni-Vincentelli³

1994

Proceedings of the 1994 ACM/IEEE Conference on Supercomputing - Supercomputing '94

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Simulating capacitive cross-talk effects in DC-coupled hybrid silicon pixel detectors

Bonvicini

Pindo

1996

Nuclear Instruments and Methods in Physics Research Section A:

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Capacitance of silicon pixels

Gorfine

Hoeferkamp

Santistevan

et al. 2001

Nuclear Instruments and Methods in Physics Research Section A:

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Capacitance measurements have been made on silicon pixel sensors of types n + on n, p + on n, and n + on p. The arrays test a variety o f implant and gap widths, and the n + on n devices test several p-stop designs. The measurements examine inter-pixel and backplane contributions and include studies of temperature dependence. Measurements were made before and after irradiation with uences relevant to LHC experiments and Fermilab Tevatron Run 2.

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Measurement And Tridimensional Simulation Of Silicon Pixel Detector Capacitance

Cited by 4 publications

References 7 publications

A parallel iterative linear solver for solving irregular grid semiconductor device matrices

A parallel iterative linear solver for solving irregular grid semiconductor device matrices

Simulating capacitive cross-talk effects in DC-coupled hybrid silicon pixel detectors

Capacitance of silicon pixels

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