Measurement of supply noise suppression by substrate and deep N-well in 90nm process

Ogasahara, Yasuhiro; Hashimoto, Masanori; Kanamoto, Toshiki; Onoye, Takao

doi:10.1109/asscc.2008.4708811

Cited by 13 publications

(6 citation statements)

References 7 publications

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“…The p-substrate makes V ss voltage stable because the V ss current is widely diffused and drained to the system ground through the resistive network of the p-substrate in addition to supply wires. In previous published works, [3], [4] referred to the relation between the p-substrate and supply noise, [5] measured smaller V ss noise than V dd noise in a twinwell structure, and our preliminary work [6] measured noise reduction by a p-substrate.…”

Section: Introductionmentioning

confidence: 67%

Supply Noise Suppression by Triple-Well Structure

Ogasahara

Hashimoto

Kanamoto

et al. 2013

IEEE Trans. VLSI Syst.

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Abstract-This brief discusses the impact of twin-and triplewell structures on power supply noise, and a substrate model for simulating the power supply noise. We observed V ss noise reduction by the resistive network of the p-substrate and V dd noise reduction by the junction capacitance of a triple-well structure on a 90-nm test chip. Measurement results also showed that the total noise reduction of a triple-well structure is superior to that of a twin-well structure. The measurement results correlate well with the results obtained from the power supply noise simulation using a hierarchical resistive mesh model. Our simulation-based verification indicates that in common CMOS design, a triplewell structure can reduce the power supply drop by 10%-40% or the decoupling capacitance area by 5%-10%. We also verified that supply drop sensitivity to variation of the well junction capacitance is sufficiently small and that supply noise reduction using a triple-well structure is robust to process variation.Index Terms-Circuit noise, noise measurement, substrate.

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Section: Introductionmentioning

confidence: 67%

Supply Noise Suppression by Triple-Well Structure

Ogasahara

Hashimoto

Kanamoto

et al. 2013

IEEE Trans. VLSI Syst.

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“…This approach can also be used to determine the effective resistance in any two layer mesh structure with different horizontal and vertical unit resistances. The effective resistance of a mesh is used in power grid analysis [5], [6], substrate analysis [7], decoupling capacitance allocation [8]- [11], power dissipation [12] and electrostatic discharge (ESD) analysis [12], and measuring resistance variations in power distribution networks [13]. The effective resistance is used to determine the effective region of a decoupling capacitor [8], [14].…”

Section: Introductionmentioning

confidence: 99%

Effective Resistance in a Two Layer Mesh

P.-Vaisband¹,

Jakushokas²,

Popovich³

et al. 2016

On-Chip Power Delivery and Management

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The effective resistance of a resistive mesh is a commonly used analogy for various scientific and engineering problems such as IR voltage drop estimation, distributed control including time synchronization and sensor localization, determining the chemical distance among multiple bonds, and finding the distance between two vertices in a graph. Resistive networks are a commonly used structure in electronics to model different elements of an integrated circuit, such as a physical substrate, an integrated circuit layout, and a power distribution network. On-chip power and ground networks are composed of orthogonal metal lines from different metal layers, and a resistive mesh is typically used to model these networks. A two layer mesh is therefore commonly used to analyze IR voltage drops and decoupling capacitor placement. A closed-form expression is described here for the effective resistance between the intersections of a two layer resistive mesh where the horizontal and vertical unit resistances are different. The physical distance between the nodes of interest and the ratio between the horizontal and vertical resistances k are included in the expression. The maximum error of the closed-form expression, as compared with the exact solution, is less than 5% for a wide range of k. The error further decreases with greater separation between the nodes of interest.

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“…Besides, the intrinsic decoupling capacitance consists of gate and PN-junction capacitances, and the PN-junction capacitance depends on the well structure. In [5], power supply noises in twin-well and triple-well structures are measured and compared. Compared to the twin-well structure, the ground bounce in the triple-well structure is larger due to the absence of the P-substrate resistive network, and the power voltage drop is smaller thanks to the increase in the PN-junction capacitance.…”

Section: Introductionmentioning

confidence: 99%

Power gating implementation for noise mitigation with body-tied triple-well structure

Takai

Hashimoto

Onoye

2011

2011 IEEE Custom Integrated Circuits Conference (CICC)

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Abstract-This paper investigates power gating implementations that mitigate power supply noise. We focus on the body connection of power-gated circuits, and examine the amount of power supply noise induced by power-on rush current and the contribution of a power-gated circuit as a decoupling capacitance during the sleep mode. To figure out the best implementation, we designed and fabricated a test chip in 65nm process. Experimental results with measurement and simulation reveal that the power-gated circuit with body-tied structure in triple-well is the best implementation from the following three points; power supply noise due to rush current, the contribution of decoupling capacitance during the sleep mode and the leakage reduction thanks to power gating.

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Measurement of supply noise suppression by substrate and deep N-well in 90nm process

Cited by 13 publications

References 7 publications

Supply Noise Suppression by Triple-Well Structure

Supply Noise Suppression by Triple-Well Structure

Effective Resistance in a Two Layer Mesh

Power gating implementation for noise mitigation with body-tied triple-well structure

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