Measuring and Predicting Temperature Distributions on FPGAs at Run-Time

Happe, Markus; Agne, Andreas; Plessl, Christian

doi:10.1109/reconfig.2011.59

Cited by 36 publications

(21 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The autonomous compute node achieves this by instantiating monitoring cores in the reconfigurable hardware that capture information about the system state, as for example thread-level performance and cache usage statistics. We also monitor the on-chip temperature distribution and use an adaptive temperature model [8] to predict future heat generation and heat flow. This enables us to avoid thermal hot-spots by proactive temperature-aware thread scheduling.…”

Section: Self-aware Hardware Software Platformmentioning

confidence: 99%

EPiCS: Engineering Proprioception in Computing Systems

Becker

Agne

Lewis

et al. 2012

2012 IEEE 15th International Conference on Computational Science and Engineering

Self Cite

View full text Add to dashboard Cite

Abstract-Modern compute systems continue to evolve towards increasingly complex, heterogeneous and distributed architectures. At the same time, functionality and performance are no longer the only aspects when developing applications for such systems, and additional concerns such as flexibility, power efficiency, resource usage, reliability and cost are becoming increasingly important. This does not only raise the question of how to efficiently develop applications for such systems, but also how to cope with dynamic changes in the application behaviour or the system environment.The EPiCS Project aims to address these aspects through exploring self-awareness and self-expression. Self-awareness allows systems and applications to gather and maintain information about their current state and environment, and reason about their behaviour. Self-expression enables systems to adapt their behaviour autonomously to changing conditions. Innovations in EPiCS are based on systematic integration of research in concepts and foundations, customisable hardware/software platforms and operating systems, and self-aware networking and middleware infrastructure. The developed technologies are validated in three application domains: computational finance, distributed smart cameras and interactive mobile media systems.

show abstract

Section: Self-aware Hardware Software Platformmentioning

confidence: 99%

EPiCS: Engineering Proprioception in Computing Systems

Becker

Agne

Lewis

et al. 2012

2012 IEEE 15th International Conference on Computational Science and Engineering

Self Cite

View full text Add to dashboard Cite

show abstract

“…In our previous work [7] we proposed self-calibrating temperature sensors based on ROs. The system contains an array of temperature sensors and calibrates them using an internal pre-calibrated thermal diode and internal regional heat-generating cores on a Virtex-6 FPGA.…”

Section: Related Workmentioning

confidence: 99%

“…Similar to [6,7,8] we use a RO combined with a timebase counter and a capture counter as temperature sensor. Furthermore, we access the temperature readings of our sen- Fig.…”

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

Exploration of ring oscillator design space for temperature measurements on FPGAs

Ruething

Agne

Happe

et al. 2012

22nd International Conference on Field Programmable Logic and Applications (FPL)

Self Cite

View full text Add to dashboard Cite

While numerous publications have presented ring oscillator designs for temperature measurements a detailed study of the ring oscillator's design space is still missing. In this work, we introduce metrics for comparing the performance and area efficiency of ring oscillators and a methodology for determining these metrics. As a result, we present a systematic study of the design space for ring oscillators for a Xilinx Virtex-5 platform FPGA.

show abstract

“…Only a few attempts to exploit Dynamic Partial Reconfiguration (DPR) available in several FPGA architectures to design adhoc countermeasures against TDFs have been proposed [Di Carlo et al 2012;Kameda et al 2012].…”

Section: Introductionmentioning

confidence: 99%

Satta

Carlo

Gambardella

Prinetto

et al. 2015

ACM Trans. Reconfigurable Technol. Syst.

View full text Add to dashboard Cite

Dependability issues due to nonfunctional properties are emerging as a major cause of faults in modern digital systems. Effective countermeasures have to be developed to properly manage their critical timing effects. This article presents a methodology to avoid transition delay faults in field-programmable gate array (FPGA)-based systems, with low area overhead. The approach is able to exploit temperature information and aging characteristics to minimize the cost in terms of performances degradation and power consumption. The architecture of a hardware manager able to avoid delay faults is presented and analyzed extensively, as well as its integration in the standard implementation design flow.

show abstract

Measuring and Predicting Temperature Distributions on FPGAs at Run-Time

Cited by 36 publications

References 9 publications

EPiCS: Engineering Proprioception in Computing Systems

EPiCS: Engineering Proprioception in Computing Systems

Exploration of ring oscillator design space for temperature measurements on FPGAs

Satta

Contact Info

Product

Resources

About