Mechanism of hot carrier induced degradation in MOSFET's

Baba, Shigeo; Kita, Akio; Ueda, Jun

doi:10.1109/iedm.1986.191298

Cited by 21 publications

(5 citation statements)

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“…Silicon on Nothing structure has better short channel effects than silicon on insulator [48]. The short channel effects (SCE's) like DIBL, threshold voltage roll off, hot carrier effects [49][50][51] are examined and several other performance parameters are compared with the conventional structure. SON structure has a major advantage of having less parasitic capacitances which can reduce the power utilization and can give the greater speed.…”

Section: Dielectric Pocket Based Structurementioning

confidence: 99%

“…Therefore, to lower down SCE's, engineering of placing the dielectric material is required. A high K dielectric concept has been implemented in conventional cylindrical surrounded MOS by the authors in [51,53]. The material having a low dielectric constant can be placed at the drain end whereas high dielectric material is placed at the source end.…”

Section: High-k Dielectric Based Structurementioning

confidence: 99%

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A pathway to improve short channel effects of junctionless based FET’s after incorporating technology boosters: a review

Narula,

Agarwal,

Verma

2024

Eng. Res. Express

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The Short Channel Effects (SCE) are becoming more prominent in Complementary Metal Oxide Semiconductor (CMOS) circuits with an introduction of nanoscale Metal Oxide Semiconductor Field Effect Transistor (MOSFET). The short channel effects (SCE’s) and fabrication challenges have provoked the researchers to think for some other technologies to enhance the market of semiconductor devices. To overcome these SCE’s, various methodologies such as multi-gate structures, material engineering, gate engineering, dielectric pockets, strain technology, high K dielectric material, heterostructures, source and drain extensions etc. have been implemented. However, at very short channel lengths, the sharp edges of doping are difficult to obtain and thus SCE’s have become so difficult to control even after the implementations of different methodologies. Therefore, a new type of technology has been introduced to overcome such pitfalls e.g. transistors without junctions. Junctionless field effect transistor (JLFET) is one of the technologies which has overcome various SCE’s. Although the research on various issues has been addressed by different authors but still there is an impediment in the commercialization of the same device. The different technology boosters have been incorporated into junctionless based devices to escalate the performance. The technology boosting aspect of junctionless FET has been reviewed in this paper which has not been considered yet. In this paper distinct technology boosters and numerous effects on junctionless devices have been studied and presented. The performance of the junctionless FET devices are studied on incorporating the different semiconductor materials, effect of strain, use of high k dielectric, use of dielectric pockets, effect of gate misalignment, use of heterostructures, silicon on nothing (SON), vertically stacked nanowires, newly proposed rectangular core-shell based junctionless FET’s and roles of various physical parameters such as temperature, nanowire widths and effect of scattering mechanism on the performance of JLFET have been addressed.

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Section: Dielectric Pocket Based Structurementioning

confidence: 99%

Section: High-k Dielectric Based Structurementioning

confidence: 99%

A pathway to improve short channel effects of junctionless based FET’s after incorporating technology boosters: a review

Narula,

Agarwal,

Verma

2024

Eng. Res. Express

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“…where the constants σ P0 and σ N0 are about 10 −15 cm 2 and 10 −17 cm 2 , respectively 37,38 . κ h and κ e are the evanescent wavectors for electrons and holes,…”

Section: /12mentioning

confidence: 99%

All-Silicon Non-Volatile Optical Memory Based on Photon Avalanche-Induced Trapping

Peng,

Yuan,

Cheung

et al. 2024

Preprint

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Implementing on-chip non-volatile optical memories has long been an actively pursued goal, promising significant enhancements in the capability and energy efficiency of photonic integrated circuits. Here, we achieve this milestone by demonstrating optical memory exclusively using the most common semiconductor material, silicon. By manipulating the photon avalanche effect, we introduce a trapping effect at the silicon-silicon oxide interface, which in turn demonstrates a non-volatile reprogrammable optical memory cell with a record-high 4-bit encoding, robust retention and endurance. This silicon avalanche-induced trapping memory provides a distinctively cost-efficient and high-reliability route to realize optical data storage in standard silicon foundry processes. A proposed in-memory computing system achieves image recognition from the MNIST database with an inference accuracy of 94.8% and energy efficiency of 1.64×1013 MAC/J.

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“…Reliability for any device is an important parameter along with optimum device performance [17]. The hot carrier effect [18,19] is caused by high electric field in the channel near the drain end, which in turn causes impact ionization. Consequently, it traps hot carriers in the dielectric which alter the electrical parameters of the device like threshold voltage, sub-threshold slope, transconductance, and carrier mobility.…”

Section: Introductionmentioning

confidence: 99%

Effect of high-k and vacuum dielectrics as gate stack on a junctionless cylindrical surrounding gate (JL-CSG) MOSFET

Sharma

Jain

Pratap

et al. 2016

Solid-State Electronics

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Mechanism of hot carrier induced degradation in MOSFET's

Cited by 21 publications

References 0 publications

A pathway to improve short channel effects of junctionless based FET’s after incorporating technology boosters: a review

A pathway to improve short channel effects of junctionless based FET’s after incorporating technology boosters: a review

All-Silicon Non-Volatile Optical Memory Based on Photon Avalanche-Induced Trapping

Effect of high-k and vacuum dielectrics as gate stack on a junctionless cylindrical surrounding gate (JL-CSG) MOSFET

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