Mechanism of nitrogen-enhanced negative bias temperature instability in pMOSFET

Tan, Shyue Seng; Chen, T. P.; Ang, C. H.; Chan, Lap

doi:10.1016/j.microrel.2004.02.015

Cited by 37 publications

(27 citation statements)

References 31 publications

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“…The parameters A and γ, however, show 5 Although negligible variation of E A versus %N in Fig. 8(b) (at 1.9 V) contradicts with the E A versus %N variation reported in [8] and [36], we identify this as a signature of negligible hole trapping in the PNO samples studied here, which have lower N 2 concentration near substrate interface [11], [20] as compared to the samples in [8] and [36]. systematic variation with %N (Fig.…”

Section: Variation In Nbti Model Parameters With %Nmentioning

confidence: 54%

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Optimization of Gate Leakage and NBTI for Plasma-Nitrided Gate Oxides by Numerical and Analytical Models

Islam

Gupta

Ahmed

et al. 2008

IEEE Trans. Electron Devices

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Abstract-Reduction in static-power dissipation (gate leakage) by using nitrided oxides comes at the expense of enhanced negative-bias temperature instability (NBTI). Therefore, determining the nitrogen content in gate oxides that can simultaneously optimize gate-leakage and NBTI degradation is a problem of significant technological relevance. In this paper, we experimentally and theoretically analyze wide range of gate-leakage and NBTI stress data from a variety of plasma-oxynitride gate dielectric devices to establish an optimization scheme for gate-leakage and NBTI degradation. Calculating electric fields and leakage current both numerically and using simple analytical expressions, we demonstrate a design diagram for arbitrary nitrogen concentration and effective oxide thickness that may be used for process and IC design.Index Terms-Gate leakage, negative-bias temperature instability (NBTI), optimization, plasma-oxynitride dielectric, quantummechanical (QM) effects, reaction-diffusion (R-D) model.

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Section: Variation In Nbti Model Parameters With %Nmentioning

confidence: 54%

“…We now consider the second aspect of our optimization problem, namely, the NBTI degradation, which has become an important reliability concern for technology nodes using EOT below 2 nm [7], [10], [20], [33]- [36]. NBTI describes the temperature-accelerated degradation in PMOS devices when it is stressed with negative gate voltage.…”

Section: Nbti Degradationmentioning

confidence: 99%

Optimization of Gate Leakage and NBTI for Plasma-Nitrided Gate Oxides by Numerical and Analytical Models

Islam

Gupta

Ahmed

et al. 2008

IEEE Trans. Electron Devices

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“…Various parameters such as threshold voltage, transconductance, or drain current, can be used as a degradatio monitor (Schlunder et al, 2005;Tan et al, 2005). We will us e the threshold voltage, which has been shown in previous section to be a ffected by NBT stressing, and also has been widely accepted as a well-suited parameter, so the device lifetime for practic power VDMOSFETs studied here will be estimated from the experimental results NBT stress-induced threshold voltage shifts.…”

Section: Extraction Of Experimental Lifetime Datamentioning

confidence: 99%

Implications of Negative Bias Temperature Instability in Power MOS Transistors

Danković¹,

Manić²,

Djorić-Veljković³

et al. 2009

Micro Electronic and Mechanical Systems

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“…These thin oxides substantially increases the vertical oxide field (E ox ) to the range of few MV/cm, which in turn can result in more severe NBTI degradations and corresponding V t increase of a transistor [3]. It was also shown that heavily nitrided oxides (mainly employed to alleviate gate leakages) can further expedite the degradation process [39].…”

Section: Introductionmentioning

confidence: 99%

NBTI induced performance degradation in logic and memory circuits: how effectively can we approach a reliability solution?

Kang

Gangwal

Park

et al. 2008

2008 Asia and South Pacific Design Automation Conference

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-This paper evaluates the severity of negative bias temperature instability (NBTI) degradation in two major circuit applications: random logic and memory array. For improved lifetime stability, we propose/select an efficient reliability-aware circuit design methodologies. Simulation results obtained from 65nm PTM node shows that NBTI induced degradation in random logic is considerably lower than that of a single transistor. As a result, simple delay guard-banding can efficiently mitigate the impact of NBTI in random logic. On the other hand, NBTI degradation in memory shows much severe effect especially when combined with the impact of random process variation, NBTI can dramatically reduce the READ stability of memory cells. Hence, aggressive design techniques such as stand-by V DD scaling or adaptive body biasing (ABB) are required in memory application to minimize the impact of NBTI.

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Mechanism of nitrogen-enhanced negative bias temperature instability in pMOSFET

Cited by 37 publications

References 31 publications

Optimization of Gate Leakage and NBTI for Plasma-Nitrided Gate Oxides by Numerical and Analytical Models

Optimization of Gate Leakage and NBTI for Plasma-Nitrided Gate Oxides by Numerical and Analytical Models

Implications of Negative Bias Temperature Instability in Power MOS Transistors

NBTI induced performance degradation in logic and memory circuits: how effectively can we approach a reliability solution?

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