Mechanism of Threshold Voltage Shift (ΔVth) Caused by Negative Bias Temperature Instability (NBTI) in Deep Sub-Micron pMOSFETs

Nano‐CMOS Scaling Problems and Implications

“…Negative bias temperature instability (NBTI) is an effect that surfaced as gate oxide thickness was scaled. Gate oxide thickness for the 130-nm technology node has already resulted in sensitivity to NBTI [18]. Any processing step that causes bond breaking will exacerbate NBTI.…”

Mechanism and process dependence of negative bias temperature instability (NBTI) for pMOSFETs with ultrathin gate dielectrics

“…Although much effort has been recently dedicated to the study of NBTI [ 1-51, the details of the degradation process are not well understood. More recently, based on the first-order electrochemical reactions at the oxide/Si interface given in [2], a mathematical model [6] has been developed to describe the NBTI degradation behavior. This paper further proposes a more generalized model, and evaluates the resistance to this degradation mode for ultrathin gate dielectrics (1.7 nm -3.3 nm) fabricated by different processes that have been used for different technologies and/or applications.…”

Extending the reliability scaling limit of gate dielectrics through remote plasma nitridation of N/sub 2/O-grown oxides and NO RTA treatment

“…On the other hand, RPN samples with high nitrogen concentration in the films show large threshold voltage shift. Based on the model proposed in[15], N,O+RPN+NO samples have the least hydrogenated trivalent silicon bonds as aresult ofsmooth interfaces passivated by NO annealing, while RpN samples with high nitrogen content (especially at oxide / Si-substrate interface) as shown inFig. 1…”