MEDUSA: A Predictable and High-Performance DRAM Controller for Multicore Based Embedded Systems

Valsan, Prathap Kumar; Yun, Heechul

doi:10.1109/cpsna.2015.24

Cited by 24 publications

(14 citation statements)

References 19 publications

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“…Independently of the aspect of performance improvement, contiguous mapping allows for better static analysability [1,3,22,25,36]. As the results show, this analysability comes at a very moderate price, the possible average performance degradation being low in most of the cases.…”

Section: Performance Comparison Of Interleaved Vs Contiguous Mappingmentioning

confidence: 93%

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Minimising Access Conflicts on Shared Multi-Bank Memory

Tretter

Giannopoulou

Baer

et al. 2017

ACM Trans. Embed. Comput. Syst.

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A common multi-core pattern consists of processors communicating through shared, multi-banked on-chip memory. Two approaches exist: Interleaved address mapping, which spreads consecutive data over all banks, and contiguous address mapping, which stores consecutive data on a single bank. In this work, we compare both approaches on the Kalray MPPA-256 platform. For contiguous mapping, we propose an algorithm, based on graph colouring techniques, to automatically perform the assignment of data blocks to memory banks with the goal of minimising access collisions and delays. Experiments with representative, parallel real-world benchmarks show that 69% of the tested configurations, when optimised for contiguous mapping by our algorithm, run up to 86% faster on average than with interleaved mapping. CCS Concepts: • Computing methodologies → Shared memory algorithms; • Computer systems organization → Embedded software; System on a chip; • Hardware → Memory and dense storage;

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Section: Performance Comparison Of Interleaved Vs Contiguous Mappingmentioning

confidence: 93%

“…This is why recent publications in that domain focus on contiguous mapping, see e.g. [1,3,22,25,36].…”

Section: Introductionmentioning

confidence: 99%

Minimising Access Conflicts on Shared Multi-Bank Memory

Tretter

Giannopoulou

Baer

et al. 2017

ACM Trans. Embed. Comput. Syst.

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“…RELATED WORK Recent literature on the design of real-time systems on multicore platforms considers main memory as a significant source of unpredictability, and an important interfering channel to mitigate. Predictable memory controllers have been proposed in [16]- [18]. OS-level techniques implementable on COTS hardware to regulate access of cores to main memory have been proposed and evaluated in [1], [11], [19], [20].…”

Section: Varying Memory Intensity Ratio M Irmentioning

confidence: 99%

Analysis of Dynamic Memory Bandwidth Regulation in Multi-core Real-Time Systems

Agrawal

Mancuso

Pellizzoni³

et al. 2018

2018 IEEE Real-Time Systems Symposium (RTSS)

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One of the primary sources of unpredictability in modern multi-core embedded systems is contention over shared memory resources, such as caches, interconnects, and DRAM. Despite significant achievements in the design and analysis of multi-core systems, there is a need for a theoretical framework that can be used to reason on the worst-case behavior of realtime workload when both processors and memory resources are subject to scheduling decisions.In this paper, we focus our attention on dynamic allocation of main memory bandwidth. In particular, we study how to determine the worst-case response time of tasks spanning through a sequence of time intervals, each with a different bandwidth-tocore assignment. We show that the response time computation can be reduced to a maximization problem over assignment of memory requests to different time intervals, and we provide an efficient way to solve such problem. As a case study, we then demonstrate how our proposed analysis can be used to improve the schedulability of Integrated Modular Avionics systems in the presence of memory-intensive workload.

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“…Three recent papers [16,18,32] have proposed mixed-criticality controllers to allow guaranteed latency bounds for critical, hard real-time requestors while optimizing average throughput for non-critical requestors. In all such proposals, noncritical requestors are scheduled according to a First-Ready, First-Come-First-Serve (FR-FCFS) arbitration which is common in COTS controllers.…”

Section: Related Workmentioning

confidence: 99%

A composable worst case latency analysis for multi-rank DRAM devices under open row policy

Pellizzoni

Guo

2016

Real-Time Syst

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As multi-core systems are becoming more popular in real-time embedded systems, strict timing requirements for accessing shared resources must be met. In particular, a detailed latency analysis for Double Data Rate Dynamic RAM (DDR DRAM) is highly desirable. Several researchers have proposed predictable memory controllers to provide guaranteed memory access latency. However, the performance of such controllers sharply decreases as DDR devices become faster and the width of memory buses is increased. High-performance Commercial-Off-The-Shelf (COTS) memory controllers in general-purpose systems employ open row policy to improve average case access latencies and memory throughput, but the use of such policy is not compatible with existing real-time controllers. In this article, we present a new memory controller design together with a novel, composable worst case analysis for DDR DRAM that provides improved latency bounds compared to existing works by explicitly modeling the DRAM state. In particular, our approach scales better with increasing memory speed by predictably taking advantage of shorter latency for access to open DRAM rows. Furthermore, it can be applied to multi-rank devices, which allow for increased access parallelism. We evaluate our approach based on worst case analysis bounds and simulation results, using both synthetic tasks and a set of realistic benchmarks. In particular, benchmark evaluations show up to 45% improvement in worst case task execution time compared to a competing predictable memory controller for a system with 16 requestors and one rank.

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MEDUSA: A Predictable and High-Performance DRAM Controller for Multicore Based Embedded Systems

Cited by 24 publications

References 19 publications

Minimising Access Conflicts on Shared Multi-Bank Memory

Minimising Access Conflicts on Shared Multi-Bank Memory

Analysis of Dynamic Memory Bandwidth Regulation in Multi-core Real-Time Systems

A composable worst case latency analysis for multi-rank DRAM devices under open row policy

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