Mellow Writes: Extending Lifetime in Resistive Memories through Selective Slow Write Backs

Zhang, Lunkai; Neely, Brian; Franklin, Diana; Strukov, Dmitri B.; Xie, Yuan; Chong, Frederic T.

doi:10.1109/isca.2016.52

Cited by 44 publications

(29 citation statements)

References 39 publications

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“…Such failures are exposed to the OS, which monitors the health of the available physical memory, detects the faulty cells, and retires the affected physical memory at granularity of small pages [24,25]. While a recent study at Facebook already reports increasing memory error rates due to DRAM technology scaling to smaller feature sizes [26], emerging memory technologies, such as 3D XPoint, are likely to have a higher incidence of memory cell failures due to lower endurance as compared to DRAM [27,28]. Hard memory faults dramatically complicate memory management not only with segments but also with large pages; e.g., by introducing an extra level of abstraction [29] and new software and hardware machinery (e.g., per-segment Bloom filters for pages with hard faults [13]).…”

Section: Disruptive Proposals Are Undesirablementioning

confidence: 99%

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Margaritov

Ustiugov

Bugnion

et al. 2019

Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture

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With explosive growth in dataset sizes and increasing machine memory capacities, per-application memory footprints are commonly reaching into hundreds of GBs. Such huge datasets pressure the TLB, resulting in frequent misses that must be resolved through a page walk-a long-latency pointer chase through multiple levels of the in-memory radix tree-based page table. Anticipating further growth in dataset sizes and their adverse * This work was done while the author was at EPFL.

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Section: Disruptive Proposals Are Undesirablementioning

confidence: 99%

Prefetched Address Translation

Margaritov

Ustiugov

Bugnion

et al. 2019

Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture

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“…Furthermore, our insights show that SCM designers can sacrifice device speed to improve other non-performance characteristics. For example, Mellow Writes [85] shows that slowing down writes can increase the lifetime of ReRAM by orders of magnitude, while Zhang et al demonstrate a similar tradeoff for PCM [86]. When considering whether or not to adopt such a technique, our performance model provides concrete evidence to architects that extended latencies can indeed be tolerated given the opportunity to amortize them with large row buffers.…”

Section: Related Workmentioning

confidence: 86%

Design guidelines for high-performance SCM hierarchies

Ustiugov¹,

Daglis²,

Picorel

et al. 2018

Proceedings of the International Symposium on Memory Systems

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With emerging storage-class memory (SCM) nearing commercialization, there is evidence that it will deliver the much-anticipated high density and access latencies within only a few factors of DRAM. Nevertheless, the latency-sensitive nature of memory-resident services makes seamless integration of SCM in servers questionable. In this paper, we ask the question of how best to introduce SCM for such servers to improve overall performance/cost over existing DRAM-only architectures. We first show that even with the most optimistic latency projections for SCM, the higher memory access latency results in prohibitive performance degradation. However, we find that deployment of a modestly sized high-bandwidth 3D stacked DRAM cache makes the performance of an SCM-mostly memory system competitive. The high degree of spatial locality that memory-resident services exhibit not only simplifies the DRAM cache's design as page-based, but also enables the amortization of increased SCM access latencies and the mitigation of SCM's read/write latency disparity.We identify the set of memory hierarchy design parameters that plays a key role in the performance and cost of a memory system combining an SCM technology and a 3D stacked DRAM cache. We then introduce a methodology to drive provisioning for each of these design parameters under a target performance/cost goal. Finally, we use our methodology to derive concrete results for specific SCM technologies. With PCM as a case study, we show that a two bits/cell technology hits the performance/cost sweet spot, reducing the memory subsystem cost by 40% while keeping performance within 3% of the best performing DRAM-only system, whereas single-level and triple-level cell organizations are impractical for use as memory replacements.• Information systems → Storage class memory; Cloud based storage; • Hardware → Memory and dense storage; KEYWORDS Storage-class memory, heterogeneous memory hierarchy, 3D stacked DRAM ACM Reference Format:

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“…Other works propose write activity reduction [24,25], where registers are allocated on CPUs to reduce costly write operations in PCM. Yet some other works propose multi-stage write operations [67,69], where a write request is served in several steps rather than in one-shot to improve performance. Qureshi et al…”

Section: Writeback Optimizationmentioning

confidence: 99%

Enabling and Exploiting Partition-Level Parallelism (PALP) in Phase Change Memories

Song

Das

Mutlu

et al. 2019

ACM Trans. Embed. Comput. Syst.

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Phase-change memory (PCM) devices have multiple banks to serve memory requests in parallel. Unfortunately, if two requests go to the same bank, they have to be served one after another, leading to lower system performance. We observe that a modern PCM bank is implemented as a collection of partitions that operate mostly independently while sharing a few global peripheral structures, which include the sense amplifiers (to read) and the write drivers (to write). Based on this observation, we propose PALP, a new mechanism that enables partition-level parallelism within each PCM bank, and exploits such parallelism by using the memory controller's access scheduling decisions. PALP consists of three new contributions. First, we introduce new PCM commands to enable parallelism in a bank's partitions in order to resolve the read-write bank conflicts, with no changes needed to PCM logic or its interface. Second, we propose simple circuit modifications that introduce a new operating mode for the write drivers, in addition to their default mode of serving write requests. When configured in this new mode, the write drivers can resolve the read-read bank conflicts, working jointly with the sense amplifiers. Finally, we propose a new access scheduling mechanism in PCM that improves performance by prioritizing those requests that exploit partition-level parallelism over other requests, including the long outstanding ones. While doing so, the memory controller also guarantees starvation-freedom and the PCM's running-average-power-limit (RAPL).We evaluate PALP with workloads from the MiBench and SPEC CPU2017 Benchmark suites. Our results show that PALP reduces average PCM access latency by 23%, and improves average system performance by 28% compared to the state-of-the-art approaches. CCS CONCEPTS• Computer systems organization → Architectures; • Hardware → Memory and dense storage.

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Mellow Writes: Extending Lifetime in Resistive Memories through Selective Slow Write Backs

Cited by 44 publications

References 39 publications

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Design guidelines for high-performance SCM hierarchies

Enabling and Exploiting Partition-Level Parallelism (PALP) in Phase Change Memories

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