MemJam: A False Dependency Attack Against Constant-Time Crypto Implementations

Moghimi, Ahmad; Eisenbarth, Thomas; Sunar, Berk

doi:10.1007/s10766-018-0611-9

Cited by 56 publications

(50 citation statements)

References 48 publications

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“…8 Related work 8.1 Microarchitectural side/covert channel attacks This paper builds on a rich literature on microarchitectural side/covert channel attacks. Many processor structures have been shown to leak privacy over these channels, including a variety of cache architectures [57, 87ś89], branch predictors [1,27], pipeline components [5,7,34], and other structures [26,33,53,63,83,85]. All these channels reveal information about data łin transit, ž i.e., being operated on by specific instructions in the sender (victim) program.…”

Section: Colocating Attacker-controlled Datamentioning

confidence: 99%

Safecracker: Leaking Secrets through Compressed Caches

Tsai

Sánchez

Fletcher

et al. 2020

Proceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Syste

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The hardware security crisis brought on by recent speculative execution attacks has shown that it is crucial to adopt a security-conscious approach to architecture research, analyzing the security of promising architectural techniques before they are deployed in hardware.This paper offers the first security analysis of cache compression, one such promising technique that is likely to appear in future processors. We find that cache compression is insecure because the compressibility of a cache line reveals information about its contents. Compressed caches introduce a new side channel that is especially insidious, as simply storing data transmits information about it.We present two techniques that make attacks on compressed caches practical. Pack+Probe allows an attacker to learn the compressibility of victim cache lines, and Safecracker leaks secret data efficiently by strategically changing the values of nearby data. Our evaluation on a proof-ofconcept application shows that, on a common compressed cache architecture, Safecracker lets an attacker compromise a secret key in under 10 ms, and worse, leak large fractions of program memory when used in conjunction with latent memory safety vulnerabilities. We also discuss potential ways to close this new compression-induced side channel. We hope this work prevents insecure cache compression techniques from reaching mainstream processors.

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Section: Colocating Attacker-controlled Datamentioning

confidence: 99%

Safecracker: Leaking Secrets through Compressed Caches

Tsai

Sánchez

Fletcher

et al. 2020

Proceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Syste

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“…Vectors 4, 5: sub-address optimizations: Numerous data oblivious codes, e.g., "constant time" cryptography [50], [51], make an assumption that modulating certain bits in a memory address (e.g., the bits indicating offset within a cache line) does not create observable behaviors. This assumption doesn't hold on some microarchitectures due to hardware optimizations such as speculative store forwarding (Vector 4) and cache banking (Vector 5), and attacks exploiting these features have been shown to lead to full cryptographic breaks [52], [53].…”

Section: B Security Issues In Existing Data Oblivious Codementioning

confidence: 99%

“…Case study: constant time AES: An important commercial use-case for data oblivious code today is "constant time" cryptography. Many papers have demonstrated how unprotected codes-e.g., T-table AES [35] and naive modular exponentiation for RSA-leak privacy over microarchitectural side channels [4], [53], [52]. As a result, practitioners use slower codes to improve security-e.g., S-box or bitslice AES [36] and montgomery ladder exponentiation for RSA.…”

Section: )mentioning

confidence: 99%

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Data Oblivious ISA Extensions for Side Channel-Resistant and High Performance Computing

Hsiung²,

El'Hajj³

et al. 2019

Proceedings 2019 Network and Distributed System Security Symposium

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Blocking microarchitectural (digital) side channels is one of the most pressing challenges in hardware security today. Recently, there has been a surge of effort that attempts to block these leakages by writing programs data obliviously. In this model, programs are written to avoid placing sensitive data-dependent pressure on shared resources. Despite recent efforts, however, running data oblivious programs on modern machines today is insecure and low performance. First, writing programs obliviously assumes certain instructions in today's ISAs will not leak privacy, whereas today's ISAs and hardware provide no such guarantees. Second, writing programs to avoid data-dependent behavior is inherently high performance overhead. This paper tackles both the security and performance aspects of this problem by proposing a Data Oblivious ISA extension (OISA). On the security side, we present ISA design principles to block microarchitectural side channels, and embody these ideas in a concrete ISA capable of safely executing existing data oblivious programs. On the performance side, we design the OISA with support for efficient memory oblivious computation, and with safety features that allow modern hardware optimizations, e.g., out-of-order speculative execution, to remain enabled in the common case. We provide a complete hardware prototype of our ideas, built on top of the RISC-V out-of-order, speculative BOOM processor, and prove that the OISA can provide the advertised security through a formal analysis of an abstract BOOM-style machine. We evaluate area overhead of hardware mechanisms needed to support our prototype, and provide performance experiments showing how the OISA speeds up a variety of existing data oblivious codes (including "constant time" cryptography and memory oblivious data structures), in addition to improving their security and portability.

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“…It is worth noting that since no shared memory exists between the victim enclave and the attacker, "Flush+Reload" [YF14] and "Flush+Flush" [GMWM16] cannot be used. According to Table 6, Bluethunder is able to recover instruction-level information, whose spatial resolution is much higher than pagelevel [GRBG18] or cache-level attacks [OST06,MWES19]. Also, since Bluethunder does not require cache eviction [OST06] or executing a large number of jump instructions for training [ERAG + 18], its detectability is low.…”

Section: Abusing Collisionsmentioning

confidence: 99%

Bluethunder: A 2-level Directional Predictor Based Side-Channel Attack against SGX

Huo

Meng

Wang

et al. 2019

TCHES

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Software Guard Extension (SGX) is a hardware-based trusted execution environment (TEE) implemented in recent Intel commodity processors. By isolating the memory of security-critical applications from untrusted software, this mechanism provides users with a strongly shielded environment called enclave for executing programs safely. However, recent studies have demonstrated that SGX enclaves are vulnerable to side-channel attacks. In order to deal with these attacks, several protection techniques have been studied and utilized.In this paper, we explore a new pattern history table (PHT) based side-channel attack against SGX named Bluethunder, which can bypass existing protection techniques and reveal the secret information inside an enclave. Comparing to existing PHT-based attacks (such as Branchscope [ERAG+18]), Bluethunder abuses the 2-level directional predictor in the branch prediction unit, on top of which we develop an exploitation methodology to disclose the input-dependent control flow in an enclave. Since the cost of training the 2-level predictor is pretty low, Bluethunder can achieve a high bandwidth during the attack. We evaluate our attacks on two case studies: extracting the format string information in the vfprintf function in the Intel SGX SDK and attacking the implementation of RSA decryption algorithm in mbed TLS. Both attacks show that Bluethunder can recover fine-grained information inside an enclave with low training overhead, which outperforms the latest PHT-based side channel attack (Branchscope) by 52×. Specifically, in the second attack, Bluethunder can recover the RSA private key with 96.76% accuracy in a single run.

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MemJam: A False Dependency Attack Against Constant-Time Crypto Implementations

Cited by 56 publications

References 48 publications

Safecracker: Leaking Secrets through Compressed Caches

Safecracker: Leaking Secrets through Compressed Caches

Data Oblivious ISA Extensions for Side Channel-Resistant and High Performance Computing

Bluethunder: A 2-level Directional Predictor Based Side-Channel Attack against SGX

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