Memory-access aware work-load distribution for peak-temperature reduction of 3D multi-core embedded systems

Memory-Aware Scheduling for Fixed Priority Hard Real-Time Computing Systems

“…By tracking the time-dependent computing and memory demands for each task, the corresponding hardware power congurations of the core and memory system can be set to reduce overall platform power and thereby improve energy efciency with minimal compromises in performance. [155,156]. Other thermal man-agement approaches for 3D architectures, such as [157], propose to reduce temperature variance and the peak temperature of a 3D multi-core processor and stacked DRAM by thermally-aware thread migration among processor cores.…”

“…Chen et al[154] characterize the thermal and performance behavior of the target architecture when the voltage and frequency levels of cores and DRAMs are synergistically controlled, targeting an architecture with multiple layers of DRAM memory. Some studies propose to manage the power and thermal parameters in 3D ICs by performing memory mapping techniques[155,156]. The research proposed in[188] describes a novel runtime system that scales the frequency of both processor and DRAM-based on the performance and power models.…”