Memory access optimizations in instruction-set simulators

Abstract

Design of programmable processors and embedded applications requires instruction-set simulators for early exploration and validation of candidate architectures. Interpretive simulators are widely used in embedded systems design. One of the key performance bottlenecks in interpretive simulation is the instruction and data memory access translation between host and target machines. The simulators must maintain and update the status of the simulated processor including memory and register values. A major challenge in the simulation is to efficiently map the target address space to the host address space. This paper presents two optimization techniques that aggressively utilize the spatial locality of the instruction and data accesses in interpretive simulation: signature based address mapping for optimizing general memory accesses; and incremental instruction fetch for optimizing instruction accesses. To demonstrate the utility of this approach we applied these techniques on SimpleScalar simulator, and obtained up to 30% performance improvement. Our techniques complement the recently proposed optimizations (JIT-CCS [1] and IS-CS [2]) and further improve the performance (up to 89%) on ARM7 and Sparc processors.

Methods for rapid selection of processors for constraint-aware embedded systems

“…In addition to these, there are commercial instruction set simulators, which In [49,50], the authors classify instruction set simulators into two categories:…”

“…interpretive simulation and compiled simulation. In compiled simulation on the other hand, the time consuming decoding step is moved from the runtime to compile time [49]. The basic flow of a compiled simulation is shown in Fig.…”