Memory analysis for H.264/AVC scalable extension encoder

Chen, Tzu‐Yu; Li, Gwo-Long; Chang, Tian-Sheuan

doi:10.1109/iscas.2009.5117760

Cited by 1 publication

(2 citation statements)

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“…Thus, we choose the frame-level coding method for our design based on the cost and memory bandwidth tradeoff. A much more complete analysis for SVC encoder with temporal scalability can be found in our previous work [2].…”

Section: Analysis Resultsmentioning

confidence: 99%

“…In the following simulation, 100 I-frames of eight sequences with different resolutions and four QPs of 8, 16, 24, and 32 are undertested. The thresholds of th4DCdom (set to 16), th4DCoff (set to 2), th8DCdom (set to 64), th8DCoff (set to 2), and th16DCoff (set to 2) are derived either from [11] or experimentally with considering the simplicity of hardware implementation. The comparison of bitrate (BR) and peak signal-to-noise ratio (PSNR) between the original result in JM12.4 [12] (with the low-complexity mode) and the proposed algorithm is listed in Table VII.…”

Section: B Simulation Resultsmentioning

confidence: 99%

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135-MHz 258-K Gates VLSI Design for All-Intra H.264/AVC Scalable Video Encoder

Chen

Shen

et al. 2013

IEEE Trans. VLSI Syst.

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To satisfy the video application diversities, an extension of H.264/advanced video coding (AVC), called scalable video coding (SVC), is designed to provide multiple demanded video data via a single video encoder. However, constructed on the fundamental of H.264/AVC, the complexity of SVC is much higher than that of H.264/AVC. In this paper, a VLSI design for all-intra scalable video encoder is proposed to aim at efficient scalable video encoding. First, the memory bandwidth requirements for several encoding methods are analyzed to find out the best encoding method which can achieve best tradeoff between internal memory usage and external memory access. Afterward, an all-intra SVC encoder combined with several advanced techniques, including fast intra prediction algorithm, efficient syntax element encoding approach in context-adaptive variable-length coding, and hardware-efficient techniques, are implemented in a macroblock (MB)-level pipeline to increase data throughput. Implementation results demonstrate that our proposed SVC encoder can process more than 594-k MBs per second, which is equivalent to the summation of 60 high-definition, 1080-p, SD 480-p, and common intermediate format frames under 135-MHz working frequency. The proposed design consumes 258-K gate counts when synthesized by 90-nm CMOS technology.Index Terms-All-intra, scalable video coding (SVC), VLSI architecture design.

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Section: Analysis Resultsmentioning

confidence: 99%

Section: B Simulation Resultsmentioning

confidence: 99%