Memory Carousel: LLVM-Based Bitwise Wear Leveling for Nonvolatile Main Memory

Abstract

Emerging non-volatile memory yields, alongside many advantages, technical shortcomings, such as reduced cell lifetime. Although many wear-leveling approaches exist to extend the lifetime of such memories, usually a trade-off for the granularity of wear-leveling has to be made. Due to iterative write schemes (repeatedly sense and write), wear-out of memory in certain systems is directly dependent on the written bit value and thus can be highly imbalanced, requiring dedicated bit-wise wear-leveling. Such a bit-wise wear-leveling so far has only be proposed together with a special hardware support. However, if no dedicated hardware solutions are available, especially for commercial off-the-shelf systems with non-volatile memories, a software solution can be crucial for the system lifetime.In this work, we propose entirely software-based bit-wise wearleveling, where the position of bits within CPU words in main memory is rotated on a regular basis. We leverage the LLVM intermediate representation to adjust load and store operations of the application with a custom compiler pass. Experimental evaluation shows that the lifetime by applying local rotation within the CPU word can be extended by a factor of up to 21×. We also show that our method can incorporate with coarser-grained wear-leveling, e.g. on block granularity and assist achievement of higher lifetime improvements.

Rapid NVM Simulation and Analysis on Single Bit Granularity Featuring Gem5 and NVMain

“…Earlier versions of this setup have been used before to implement Wear-leveling solutions in Unikraft on various occasions [9] [8]. Since Unikraft is open-source and can be build on the host machine, even compiler solutions can be integrated [11]. All benchmarks, presented in Section VI, are ported to work with Unikraft.…”

“…While there are software-based approaches at different layers for different granularity [3], [11], [15], [16], [18], [19], [24], most of them rely on their own in-house methods to validate their presented methods. In addition, we consider them lacking for at least one of the following reasons:…”

“…Our previous contributions to wear-leveling and memory access tracing [8]- [10] use an evaluation setup, assuming whole memory word accesses. In later work [11] this setup was further extended to generate memory traces with single bit granularity under the assumption of iterative write schemes. Also, compiler solutions were added to the tool chain.…”