Memory-cell layout as a factor in the single-event-upset susceptibility of submicron dice CMOS SRAM

Stenin, V. Ya.; Cherkasov, I. G.

doi:10.1134/s1063739711030097

Cited by 8 publications

(5 citation statements)

References 1 publication

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“…2 to make it more helpful). Stenin and Cherkasov [9] reported an experimental investiga tion into the single event upset susceptibility of dual path D flip flops as dependent on converter spacing in the context of static random access memory imple mented in a 0.18 μm CMOS technology and exposed to 1 GeV protons. The upset rate was found to decrease by a factor of 5.5 to 15 (depending on the supply voltage) when L 1,2 and L 3,4 were both increased from 0.9 to 2.5 μm.…”

Section: Layoutmentioning

confidence: 99%

Single-event-upset susceptibility simulation of sub-1-μm CMOS dual-path inverters

Ol’chev

Stenin

2012

Russ Microelectron

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A computer simulation is run to estimate the single event upset susceptibility of dual path invert ers implemented in 0.18 μm CMOS technology, which are known to tolerate much higher photocurrent pulses as compared with conventional designs. Relations are established between the peak photocurrent and total collected charge associated with a single nuclear particle on the one hand and the peak voltage response on the other. In the first of two identical inverters connected in cascade, the peak photocurrent is found to be 1.1 to 2.2 fold higher than the output current at the instant of extreme output voltage, with the coefficient depending on the transistor parameters of the inverter. The critical charge to upset is found to be 10 to 15 fold higher than for conventional designs.

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Section: Layoutmentioning

confidence: 99%

Single-event-upset susceptibility simulation of sub-1-μm CMOS dual-path inverters

Ol’chev

Stenin

2012

Russ Microelectron

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“…However, the separation of paired pairs of the DICE cell is accompanied by a increase in the capacitive coupling of the buses connecting the paired elements, which decreases the upset tolerance. Figure 1 shows the scheme of the DICE memory cell [9] based on the two phase D trigger with the cross link of outputs-inputs of two phase inverters, which in turn have cross links of inputs of constituent paired elements-converters [6]. The first inverter forms converters K1 and K2, and the second inverter forms converters K3 and K4.…”

Section: Introductionmentioning

confidence: 99%

“…The development of upset tolerant CMOS VLSI RAMs requires the application of a spe cial circuit [2], constructive and technological [3,4], as well as system and algorithmic [5] measures for decreas ing the sensitivity to the effect of separate nuclear parti cles. The circuit measures are the two phase CMOS logics [6], which involves the DICE memory cells [7][8][9]. In the elements of the two phase logics under the effect of the local current pulse on one of differential paired parts of the element, the signal difference appears in its symmetric assemblies, which prevents the variation in the logic state of the element.…”

Section: Introductionmentioning

confidence: 99%

“…To obtain such a protective effect with respect to the local effect of separate nuclear particles, the spatial separation of paired sensitive assemblies of two phase elements to a sufficient distance is necessary. The experimental inves tigation of the static CMOS RAM based on the DICE memory cells with the 0.18 μm design rule under the effect of protons with an energy of 1 GeV [9] showed that the average SEU cross section per bit for a dis tance between the sensitive regions of 2.5 μm was 0.7 × 10 -15 cm 2 /bit, and for a distance of 0.9 μm it was 1.1 × 10 -14 cm 2 /bit; they differed by a factor of 15. However, the separation of paired pairs of the DICE cell is accompanied by a increase in the capacitive coupling of the buses connecting the paired elements, which decreases the upset tolerance.…”

Section: Introductionmentioning

confidence: 99%

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Simulation of the local effect of nuclear particles on 65-nm CMOS DICE memory cells

Stenin

Stepanov

2012

Russ Microelectron

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Sensitivity characteristics of the DICE CMOS memory cells as two phase D triggers with the 65 nm design rule. The dependences of critical values of the amplitudes of current pulses causing the failures during recording and storing the data are determined for various coupling capacitances of differential inputs of two phase inverters in the composition of the memory cell. The following limitations for the values of these capaci tances are established: 0.4-0.5 fF for memory cells based on NMOS transistors with a channel width of 400 nm and 0.2-0.3 fF for NMOS transistors with a channel width of 120 nm. Evaluations of critical integral charges that characterize the failure tolerance under the effect of separate nuclear particles give correspondingly values of 25-20 fC, which is larger by a factor of 8 compared with the 6 transistor CMOS memory cells.

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“…The upset rate of CMOS triggers and the memory cells based on them, potentially resistant to impacts of single nuclear particles can be reduced [4][5][6][7] by increasing the distance between the sensitive nodes. It was established [4,5] that redundant distance of 1 μm between the sensitive nodes of the memory cells and triggers of the DICE type with project standards of CMOS equal to 28-65 nm, under the impact of neutrons and protons, the upset rate is reduced by a factor of 100 compared to the rate when this distance is 100-300 nm, which is typical for traditional commercial technology.…”

Section: Introductionmentioning

confidence: 99%

Upset-resilient RAM on STG DICE memory elements with the spaced transistors into two groups

2016

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Abstract⎯The first experimental test of new DICE memory cells with the transistors spaced into two groups (Spaced Transistor Groups DICE-STG DICE), composed on a 65-nm CMOS static RAM proved their high upset resilience. The STG DICE memory cells have two communication wires between the two groups of transistors that made it possible to use the striping of groups of transistors to increase the distances between sensitive nodes of cells up to 2.32-3.09 μm at a small increase in cell area. The blocks of 65-nm 128 × 32-bit CMOS RAM cache and 32 × 64-bit multiport RAM based on the STG DICE cells are characterized by upset thresholds lying in the range of 3.55-4.05 nJ of the laser pulse energy with a pulse duration of 70 ps and diameter of the spot of 3.5 μm. These threshold values exceed the upset thresholds of 65-nm CMOS RAM on 6T memory cells by factors of 20 for RAM cache and 3.5 for multiport RAM. In STG DICE RAM multiple upsets are absent in contrast to RAM based on 6T-cells.

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Memory-cell layout as a factor in the single-event-upset susceptibility of submicron dice CMOS SRAM

Cited by 8 publications

References 1 publication

Single-event-upset susceptibility simulation of sub-1-μm CMOS dual-path inverters

Single-event-upset susceptibility simulation of sub-1-μm CMOS dual-path inverters

Simulation of the local effect of nuclear particles on 65-nm CMOS DICE memory cells

Upset-resilient RAM on STG DICE memory elements with the spaced transistors into two groups

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