Memory characteristics of an MOS capacitor structure with double-layer semiconductor and metal heterogeneous nanocrystals

Henan, Ni; Wu, Liangcai; Song, Zhitang; Hu, Chun

doi:10.1088/1674-4926/30/11/114003

Cited by 9 publications

(3 citation statements)

References 15 publications

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“…The amount of charges stored in the device is proportional to the magnitude of the V FB shift. 39 At V g ¼ À8 V, the V FB moves to the negative V g direction and with the increase of the stress time, the V FB shift increases, e.g., À0.4 V after 1 ms and À1.01 V after 30 s. After 30 s, the hole trapping is saturated. The similar time-dependent electron trapping trend is observed.…”

Section: Resultsmentioning

confidence: 97%

Memory functions of nanocrystalline cadmium selenide embedded ZrHfO high-k dielectric stack

Lin

Kuo

2014

Journal of Applied Physics

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Metal-oxide-semiconductor capacitors made of the nanocrystalline cadmium selenide nc-CdSe embedded Zr-doped HfO2 high-k stack on the p-type silicon wafer have been fabricated and studied for their charge trapping, detrapping, and retention characteristics. Both holes and electrons can be trapped to the nanocrystal-embedded dielectric stack depending on the polarity of the applied gate voltage. With the same magnitude of applied gate voltage, the sample can trap more holes than electrons. A small amount of holes are loosely trapped at the nc-CdSe/high-k interface and the remaining holes are strongly trapped to the bulk nanocrystalline CdSe site. Charges trapped to the nanocrystals caused the Coulomb blockade effect in the leakage current vs. voltage curve, which is not observed in the control sample. The addition of the nanocrystals to the dielectric film changed the defect density and the physical thickness, which are reflected on the leakage current and the breakdown voltage. More than half of the originally trapped holes can be retained in the embedded nanocrystals for more than 10 yr. The nanocrystalline CdSe embedded high-k stack is a useful gate dielectric for this nonvolatile memory device.

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Section: Resultsmentioning

confidence: 97%

Memory functions of nanocrystalline cadmium selenide embedded ZrHfO high-k dielectric stack

Lin

Kuo

2014

Journal of Applied Physics

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“…As an example, the devices were deposited using the low-pressure chemical vapor deposition (LPCVD) method; thermally recrystallized Si-NCs that were introduced in SiO 2 can be characterized by the memory window manifested as the change of V fb under V p/e of the order of 1.6 V and 3.5 V, for a bipolar asymmetric and unipolar sequence of program and erase pulses, respectively [19]. In the case of Si clusters obtained through thermal evaporation, the memory window of the order of 5.1 V was shown [20]. If one takes into account the threshold voltage (V t ) shift, the values of the order of 1.5 V [21] or 1-3 V [22] have been reported.…”

Section: Resultsmentioning

confidence: 99%

Silicon-Carbide (SiC) Nanocrystal Technology and Characterization and Its Applications in Memory Structures

et al. 2020

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Colloidal cubic silicon-carbide nanocrystals have been fabricated, characterized, and introduced into metal–insulator–semiconductor and metal–insulator–metal structures based on hafnium oxide layers. The fabricated structures were characterized through the stress-and-sense measurements in terms of device capacitance, flat-band voltage shift, switching characteristics, and retention time. The examined electrical performance of the sample structures has demonstrated the feasibility of the application of both types of structures based on SiC nanoparticles in memory devices.

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“…Among several materials introduced to emerging technologies, silicon nanocrystals (Si‐NCs) embedded in dielectric layers have been extensively studied due to their promising applications in the field of silicon optoelectronics and photonics . The applications of Si‐NCs were already shown in field‐effect light‐emitting devices (FELEDs), photovoltaics, and memory structures based onto photoluminescence (PL) or non‐volatile semiconductor memory (NVSM) devices . Various fabrication methods have been used to obtain Si‐NCs with the possibility to control their stoichiometry and/or thickness including reactive magnetron sputtering, thermal beam evaporation, or CVD‐based processes …”

Section: Introductionmentioning

confidence: 99%

Stress‐and‐Sense Investigation of Memory Effect in Si‐NCs MIS Structures

Mazurak

Jaśiński

Mroczynski

2018

Physica Status Solidi (b)

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Silicon nanocrystals have been recently investigated for potential applications in modern silicon optoelectronics and photonics. In this work, co-doped silicon nanocrystals embedded in hafnium oxide thin films have been introduced to metal-insulator-semiconductor (MIS) structures. The fabricated test devices are investigated for the nanocrystals charging effect and the charge retention properties parametrized by flat-band voltage shift. Electrical measurements including the stress-and-sense procedure are carried out. The effect of bias parameters on memory effect is discussed in terms of device capacitance, flat-band voltage shift, and retention time. The reported retention of flat-band voltage values extrapolated to 10 years seems to be promising for future applications in memory devices.

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Memory characteristics of an MOS capacitor structure with double-layer semiconductor and metal heterogeneous nanocrystals

Cited by 9 publications

References 15 publications

Memory functions of nanocrystalline cadmium selenide embedded ZrHfO high-k dielectric stack

Memory functions of nanocrystalline cadmium selenide embedded ZrHfO high-k dielectric stack

Silicon-Carbide (SiC) Nanocrystal Technology and Characterization and Its Applications in Memory Structures

Stress‐and‐Sense Investigation of Memory Effect in Si‐NCs MIS Structures

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