Memory Controller with Adaptive ECC for Reliable System Operation

Stefani, Marco; Marcon, César; Silva, Felipe; Silveira, Jarbas

doi:10.1109/sbcci60457.2023.10261959

Cited by 1 publication

(2 citation statements)

References 18 publications

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“…La idea de utilizar diferentes mecanismos de tolerancia a fallos en un sistema y emplear solo uno de ellos es relativamente común. Por ejemplo, [24] propone un método adaptativo para tolerar fallos en memorias que implementa tres tipos diferentes de ECC, como son el bit de paridad, un código de Hamming y un código LPC (Linear Product Code). El hecho de tener diferentes tipos de ECC implica, por un lado, que cada ECC tiene un número diferente de bits de paridad, y, por otro lado, que hay que recodificar los datos cada vez que se cambia de ECC.…”

Section: Trabajos Previos De Tolerancia a Fallos Adaptativaunclassified

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A Proposal of an ECC-based Adaptive Fault-Tolerant Mechanism for 16-bit data words

Gracia-Morán,

Saiz-Adalid,

Baraza-Calvo

et al. 2024

IEEE Latin Am. Trans.

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Actual memory systems provide large storage capacity thanks to the integration scale level achieved in CMOS technology. This increment in storage capacity comes with an augment on their fault rate. In this way, the probability of experiencing Single or Multiple Cell Upsets has risen. Error Correction Codes (ECC) are a fault-tolerant mechanism broadly employed to protect memory systems. Usually, an ECC-based fault tolerance mechanism is designed with fixed correction and detection capabilities. However, in some contexts, current memory systems can suffer a variable fault rate during their operation. Thus, it seems very interesting that this fault-tolerant mechanism would be able to adapt to these variable fault conditions. This work proposes an Adaptive Fault-Tolerant mechanism based on ECC. This mechanism can adapt to different fault conditions, being able to correct and/or detect single and multiple bits in error. The Adaptive Fault-Tolerant mechanism proposed uses a unique encoder and various decoders. Therefore, there is no need to re-encode the data to change the error coverage since the unique encoder and the equal redundancy are the same regardless of the fault tolerance required. In addition, we have studied the area, delay, and power consumption overheads produced by the inclusion of the redundant bits, the encoder, and the decoders of the ECC in a computer system.

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Section: Trabajos Previos De Tolerancia a Fallos Adaptativaunclassified

“…En cuanto al número de bits redundantes, nuestra propuesta utiliza 8 bits de código para 16 bits de datos, formando un ECC (24,16). Si tenemos en cuenta que sólo se utiliza un codificador, todos los decodificadores que se implementen utilizarán el mismo número de bits redundantes.…”

Section: A Definición Del Sistemaunclassified

A Proposal of an ECC-based Adaptive Fault-Tolerant Mechanism for 16-bit data words

Gracia-Morán,

Saiz-Adalid,

Baraza-Calvo

et al. 2024

IEEE Latin Am. Trans.

View full text Add to dashboard Cite

show abstract

Memory Controller with Adaptive ECC for Reliable System Operation

Cited by 1 publication

References 18 publications

A Proposal of an ECC-based Adaptive Fault-Tolerant Mechanism for 16-bit data words

A Proposal of an ECC-based Adaptive Fault-Tolerant Mechanism for 16-bit data words

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